The key hardware difference between a vector processor and an array processor is that:

A vector processor pipelines elements through one arithmetic unit; an array processor uses many processing elements operating in the same cycle

A vector processor has no arithmetic pipeline at all

An array processor is a subclass of MIMD

There is no meaningful difference between the two

Compared to a time-shared common bus, a crossbar switch interconnection:

Allows full simultaneous connectivity but its switch count grows as processors times memories

Cannot support more than one simultaneous transfer

Cache coherence in a shared-memory multiprocessor guarantees primarily that:

Every processor eventually sees a consistent value for any single memory location

All memory accesses across different locations happen in one globally agreed order

No processor may ever cache any data

Only one processor may run at a time

A snooping cache-coherence protocol requires:

A shared bus or medium that every cache can observe all traffic on

A central directory tracking every cache's contents

No interconnect at all between processors

Exactly two processors, never more

The primary reason chip designers moved to multicore processors rather than continuing to raise a single core's clock frequency is:

Power dissipation grows super-linearly with clock frequency (the power wall)

Multiple cores are always cheaper to fabricate

Single cores cannot execute any instruction faster than 1 GHz

Multicore eliminates the need for cache entirely

Which of the following are true of message-passing multiprocessor systems, as distinct from shared-memory systems? (More than one option may be correct.)

Processors communicate purely by sending and receiving explicit messages

There is no shared memory location for two processors to race on

Cache coherence protocols are irrelevant to their basic communication model

Processors communicate purely by sending and receiving explicit messages

There is no shared memory location for two processors to race on

They require semaphores on shared variables exactly as shared-memory systems do

Cache coherence protocols are irrelevant to their basic communication model

Pipeline and Vector Processing, and Multiprocessors

The course's pipelining chapter covers instruction pipelining, hazards and speedup. NET's syllabus names two things beyond that: vector and array processors, a different style of parallelism from pipelining, and multiprocessor systems — their interconnection structures, arbitration, communication and synchronisation, and cache coherence. This chapter covers both.

Parallel Processing and Vector/Array Processors

Flynn's classification sorts machines by instruction and data streams: SISD (a conventional uniprocessor), SIMD (a single instruction applied simultaneously across many data elements — the vector/array processor's own class), MISD (rare; multiple instructions on the same data stream, seen mainly in fault-tolerant pipelines) and MIMD (independent instruction streams over independent data — general multiprocessors). A vector processor operates on entire vectors (arrays of numbers) with single instructions (e.g. ADD V1, V2, V3 adds corresponding elements of two vectors), pipelining the vector's elements through one arithmetic pipeline rather than issuing one instruction per element; an array processor instead uses many parallel processing elements (a genuinely parallel, not pipelined, SIMD structure) each operating on its own data under one shared control unit's common instruction.

🎯 Vector pipelining is not the same speedup mechanism as array parallelism

A vector processor still processes elements through ONE pipeline, one after another, but overlaps their stages (so a result emerges every cycle once the pipeline fills, even though each element takes several cycles start to finish). An array processor genuinely computes on MANY elements in the SAME cycle, one per processing element. Both are SIMD in Flynn's sense, but their hardware and their speedup limits are different — a vector pipeline's speedup saturates with pipeline depth and vector length, an array processor's with the number of processing elements.

Multiprocessor Characteristics and Interconnection Structures

Interconnection structures, ranked by scalability against cost
Structure	How it connects processors and memory	Trade-off
Time-shared common bus	All processors and memory modules share one bus, arbitrated so only one transfer happens at a time.	Cheapest, but the bus is a single bottleneck and a single point of failure.
Crossbar switch	Every processor connects to every memory module through its own switch point.	Full simultaneous connectivity, but switch count grows as (processors × memories) — expensive to scale.
Multistage interconnection network	Several stages of small switches (e.g. 2x2) route a request from any processor to any memory.	Middle ground: fewer switches than a full crossbar, at the cost of possible blocking/contention between requests.

Interprocessor arbitration: when two or more processors contend for the same shared resource (a bus, a memory module), an arbitration scheme (fixed priority, round-robin, or a distributed protocol) grants access to exactly one at a time, preventing two simultaneous transfers from corrupting each other.
Interprocessor communication and synchronisation: shared-memory systems communicate through common memory locations directly, guarded by locks/semaphores for mutual exclusion; message-passing systems have no shared memory and communicate purely by sending/receiving explicit messages — a fundamentally different programming model with no race conditions on shared data because there IS no shared data.

Cache Coherence

In a shared-memory multiprocessor, each processor typically has its own private cache. Cache coherence is the guarantee that every processor sees a consistent view of memory — specifically, that a write by one processor is eventually (and in a well-defined order) visible to reads by every other processor, and that no two processors' caches simultaneously hold different values for the same memory location as valid. Two families of protocols enforce this: snooping protocols, where every cache monitors ("snoops") a shared bus for other processors' writes and invalidates or updates its own copy accordingly — practical only when a shared bus exists and all caches can see all traffic; and directory-based protocols, where a central or distributed directory tracks which caches hold a copy of each block and sends targeted invalidation/update messages only to those caches — necessary once the interconnect is not a single shared bus that every cache can snoop (e.g. a multistage network), since broadcasting every write to every cache would not scale.

⚠️ Coherence is about one memory location; consistency is about the order across locations

Cache coherence guarantees agreement on the value of any SINGLE location. Memory consistency models (sequential consistency, relaxed models) additionally specify the allowed ORDERING of operations on DIFFERENT locations as seen by different processors — a strictly separate and harder guarantee that coherence alone does not provide. NET-level questions typically test the coherence definition and the snooping-versus-directory distinction rather than consistency models.

Multicore Processors

A multicore processor places two or more independent processing cores on a single chip, typically sharing an on-chip last-level cache and the memory interface while each core has its own private L1 (and often L2) cache — this is a shared-memory MIMD system at chip scale, so cache coherence is required on-chip exactly as it is between separate chips.
Multicore's motivation over pushing a single core's clock faster: power dissipation grows super-linearly with clock frequency, so beyond a point adding cores at a lower per-core frequency gives more total throughput per watt than one very fast core — the well-known 'power wall' that ended the era of frequency scaling alone.

Key takeaways

Flynn's classification: SISD, SIMD (vector/array processors), MISD (rare), MIMD (general multiprocessors) — sorted by instruction and data stream counts.
A vector processor pipelines elements through one arithmetic unit; an array processor computes on many elements genuinely in parallel across many processing elements — both SIMD, different hardware and different speedup limits.
A common bus is cheap but a bottleneck; a crossbar gives full connectivity at quadratic switch cost; a multistage network is the practical middle ground.
Cache coherence guarantees a consistent view of each memory location across caches; snooping protocols need a shared, all-visible bus, directory-based protocols scale beyond one.
Multicore processors are on-chip shared-memory MIMD systems, motivated by the power wall that made adding cores more efficient than raising one core's clock further.

Practice questions (8)

Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.

In Flynn's classification, a vector processor applying one instruction across many data elements is:
1. SIMD
2. SISD
3. MISD
4. MIMD
Show answer
Answer: A — SIMD
Single Instruction, Multiple Data — one instruction stream applied across many data elements — is exactly SIMD, the class both vector and array processors belong to.
The key hardware difference between a vector processor and an array processor is that:
1. A vector processor pipelines elements through one arithmetic unit; an array processor uses many processing elements operating in the same cycle
2. A vector processor has no arithmetic pipeline at all
3. An array processor is a subclass of MIMD
4. There is no meaningful difference between the two
Show answer
Answer: A — A vector processor pipelines elements through one arithmetic unit; an array processor uses many processing elements operating in the same cycle
Both are SIMD, but a vector machine achieves throughput by overlapping the stages of ONE pipeline processing elements sequentially, while an array machine achieves it with genuinely parallel processing elements computing simultaneously.
Compared to a time-shared common bus, a crossbar switch interconnection:
1. Allows full simultaneous connectivity but its switch count grows as processors times memories
2. Is always cheaper to build
3. Cannot support more than one simultaneous transfer
4. Has no scaling cost at all
Show answer
Answer: A — Allows full simultaneous connectivity but its switch count grows as processors times memories
A crossbar gives every processor its own switch point to every memory module, so many transfers proceed simultaneously — at the cost of a switch count that grows as the product of processor and memory counts, which becomes expensive at scale.
Cache coherence in a shared-memory multiprocessor guarantees primarily that:
1. Every processor eventually sees a consistent value for any single memory location
2. All memory accesses across different locations happen in one globally agreed order
3. No processor may ever cache any data
4. Only one processor may run at a time
Show answer
Answer: A — Every processor eventually sees a consistent value for any single memory location
Coherence is a per-location guarantee; the ordering guarantee across DIFFERENT locations is the separate, stronger concern of a memory consistency model.
A snooping cache-coherence protocol requires:
1. A shared bus or medium that every cache can observe all traffic on
2. A central directory tracking every cache's contents
3. No interconnect at all between processors
4. Exactly two processors, never more
Show answer
Answer: A — A shared bus or medium that every cache can observe all traffic on
Snooping relies on every cache being able to observe every other cache's bus traffic to detect writes and invalidate/update its own copy; this scales only while a shared, all-visible bus exists, which is why directory-based schemes are used beyond it.
The primary reason chip designers moved to multicore processors rather than continuing to raise a single core's clock frequency is:
1. Power dissipation grows super-linearly with clock frequency (the power wall)
2. Multiple cores are always cheaper to fabricate
3. Single cores cannot execute any instruction faster than 1 GHz
4. Multicore eliminates the need for cache entirely
Show answer
Answer: A — Power dissipation grows super-linearly with clock frequency (the power wall)
Beyond a point, pushing clock frequency higher costs disproportionately more power per unit of extra performance, so distributing work across multiple lower-frequency cores gives more throughput per watt — the power wall.
Which of the following are true of message-passing multiprocessor systems, as distinct from shared-memory systems? (More than one option may be correct.)
1. Processors communicate purely by sending and receiving explicit messages
2. There is no shared memory location for two processors to race on
3. They require semaphores on shared variables exactly as shared-memory systems do
4. Cache coherence protocols are irrelevant to their basic communication model
Show answer
Answer: A — Processors communicate purely by sending and receiving explicit messages; B — There is no shared memory location for two processors to race on; D — Cache coherence protocols are irrelevant to their basic communication model
Message passing is a fundamentally different model with no shared address space, so there is nothing to race on and no shared variable needing a semaphore in the shared-memory sense — coherence protocols, which exist to keep shared memory's cached copies consistent, simply do not apply to it.
Name the term for the phenomenon where power dissipation grows super-linearly with clock frequency, which is the main reason processor design moved towards multiple cores instead of ever-higher single-core clocks.
Numerical answer — type the value.
Show answer
Answer: power wall
The 'power wall' is the standard name for this limit; it, alongside the memory wall and instruction-level-parallelism wall, is one of the three walls commonly cited for why single-thread performance scaling slowed and multicore designs took over.