Register Transfer Language, Microoperations and Programming the Basic Computer

The course's Computer Organisation chapter treats the data path and control unit through cycle counts and CPI. NET's syllabus names two things below that level: register-transfer notation itself (RTL, bus and memory transfers, arithmetic, logic and shift microoperations) and programming the basic computer in machine and assembly language (program loops, subroutines, I/O programming), in the style of Mano's classic basic-computer model. This chapter covers both.

Register Transfer Language and Bus Transfers

Register Transfer Language (RTL) describes micro-level data movement with a compact notation: R2 ← R1 means the contents of register R1 are transferred into R2 (a copy, not a move — R1 is unchanged); a conditional transfer is written If (P = 1) then (R2 ← R1), or in RTL shorthand P: R2 ← R1, where P is a control condition (often a single control-unit signal) that gates the transfer for exactly one clock pulse. Because a computer has many registers but typically one common data bus, register transfers are multiplexed onto it: a set of select lines chooses which register's output drives the bus, and a destination register's load-enable line is asserted for the transfer to actually be clocked in — output selection and destination selection are independent decisions, both needed for a bus transfer to take place.

⚠️ A register transfer is unconditional in hardware even when written conditionally
P: R2 ← R1 does not mean R1's value is examined and copied only if P holds in some software sense — it means the AND of the clock and P physically gates whether the load-enable pulse reaches R2's flip-flops that cycle. When P = 0, R2 simply keeps its previous value; nothing is 'skipped', a whole clock edge that could have loaded R2 simply does not.

Arithmetic, Logic and Shift Microoperations

  • Arithmetic microoperations: addition, subtraction (via 2's complement — add the complement, no separate subtractor circuit needed), increment, decrement. A single adder-subtractor unit implements both add and subtract by complementing one operand and setting the carry-in, controlled by one mode line.
  • Logic microoperations: bitwise AND, OR, XOR, NOT/complement applied independently to each bit pair — used for masking (AND with a mask clears unwanted bits), setting bits (OR), and selective complementing (XOR with a mask).
  • Shift microoperations: logical shift (fills with 0), arithmetic shift (preserves the sign bit on a right shift, treating the value as signed), and circular/rotate shift (the bit shifted out re-enters at the other end) — each usable for multiplication/division by powers of two (arithmetic shift) or for serial data movement (logical/circular).

Basic Computer Organisation, Instruction Cycle and Interrupt

The classic basic-computer model has one accumulator (AC), a memory-address register (MAR), a memory-buffer/data register (MBR/DR), a program counter (PC), an instruction register (IR), and memory-reference, register-reference and input-output instruction formats distinguished by an opcode field and an addressing-mode (direct/indirect) bit. Every instruction executes an instruction cycle: fetch (MAR ← PC, IR ← M[MAR], PC ← PC + 1), decode the opcode, compute the effective address (an extra memory read if the addressing mode is indirect), then execute. After execution, the control unit checks the interrupt flip-flop; if set, it stores the return address, disables further interrupts, and branches to the interrupt-service routine — this check is why an interrupt is never noticed mid-instruction, only at instruction boundaries.

ℹ️ Direct vs indirect addressing costs one extra memory access
In direct addressing the instruction's address field IS the operand's address. In indirect addressing the address field points to a memory word that itself holds the operand's address — one extra read is needed to fetch that pointer before the operand can be fetched, which is exactly the same extra-access cost the GATE-side chapter counts for addressing modes generally.

Machine and Assembly Language, Program Loops and Subroutines

  • Assembler: translates symbolic assembly-language mnemonics (LDA, ADD, STA, BUN, BSA...) into the machine's binary opcodes in two passes — the first pass builds a symbol table of labels and their addresses, the second generates the actual binary using that table, which is why a forward reference (a jump to a label defined later in the program) is resolvable at all.
  • Program loops: a counter is initialised, decremented (or incremented) each pass, and tested — the standard pattern is initialise, body, decrement-and-branch-if-not-zero, which is exactly a hardware-level for-loop.
  • Subroutines: a Branch-and-Save-return-address instruction (BSA) stores the return address (PC's current value) at the subroutine's first memory location and sets PC to the next location, so the subroutine's own last instruction is an indirect branch through that saved location — this is the pre-stack mechanism a hardware call/return implements, and it fails for recursion because there is only one saved slot per subroutine, not a stack of them.
  • I/O programming: programmed I/O polls a device's status flag in a tight loop before transferring one word at a time — simple but wastes CPU cycles busy-waiting, which is exactly the motivation for interrupt-driven I/O and DMA covered under Input-Output Organisation.

Key takeaways

  • RTL notation like P: R2 ← R1 describes a hardware-gated copy, not a software conditional — when P = 0 nothing happens, R2 simply keeps its old value.
  • Arithmetic microoperations use 2's-complement addition for subtraction with one adder-subtractor; logic microoperations are independent bitwise operations; shifts are logical, arithmetic (sign-preserving) or circular.
  • The instruction cycle is fetch, decode, compute effective address (extra access if indirect), execute, then check the interrupt flip-flop — interrupts are only ever noticed at instruction boundaries.
  • A two-pass assembler resolves forward references via a symbol table built in its first pass.
  • BSA-style subroutine linkage stores one return address per subroutine and cannot support recursion, unlike a stack-based call mechanism.

Practice questions (9)

Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.

  1. In the register transfer statement P: R2 ← R1, if the control condition P is 0 during a given clock cycle:

    1. R2 retains its previous value; the transfer simply does not happen that cycle
    2. R1 is cleared to zero
    3. The transfer happens anyway, but is marked invalid
    4. A hardware fault is raised
    Show answer

    Answer: A — R2 retains its previous value; the transfer simply does not happen that cycle

    P physically gates the load-enable pulse to R2's flip-flops; when it is 0 the load simply does not occur that cycle and R2 is unaffected.

  2. A single adder-subtractor circuit can perform both addition and subtraction because:

    1. Subtraction is implemented as addition of the 2's complement of one operand
    2. It contains two entirely separate circuits internally
    3. Subtraction is only possible via software emulation
    4. It uses floating-point representation internally
    Show answer

    Answer: A — Subtraction is implemented as addition of the 2's complement of one operand

    Complementing one operand and setting carry-in to 1 turns the adder into a subtractor with no separate circuitry, controlled by a single mode line.

  3. In the basic-computer instruction cycle, indirect addressing compared to direct addressing requires:

    1. One extra memory access to fetch the actual operand address
    2. No memory access at all
    3. Two extra registers
    4. A separate ALU
    Show answer

    Answer: A — One extra memory access to fetch the actual operand address

    The address field points to a memory word holding the operand's real address, so one extra read is needed to dereference that pointer before the operand itself can be fetched.

  4. An interrupt requested during instruction execution is typically serviced:

    1. Only after the current instruction completes, at an instruction boundary
    2. Immediately, interrupting the current microoperation mid-way
    3. Only at the start of the next program, never mid-program
    4. Never, unless the programmer explicitly polls for it
    Show answer

    Answer: A — Only after the current instruction completes, at an instruction boundary

    The control unit checks the interrupt flip-flop only after the execute phase of the current instruction, so an interrupt is always noticed at an instruction boundary and never mid-instruction.

  5. A two-pass assembler needs two passes chiefly because:

    1. A forward reference to a label defined later needs the symbol table built in pass one before code can be generated in pass two
    2. Machine code must always be generated twice for reliability
    3. The first pass compiles and the second pass interprets
    4. It has nothing to do with labels at all
    Show answer

    Answer: A — A forward reference to a label defined later needs the symbol table built in pass one before code can be generated in pass two

    Without a completed symbol table, a branch to a label appearing later in the source cannot yet be resolved to an address — pass one builds that table, pass two uses it.

  6. The BSA (branch-and-save-return-address) subroutine linkage mechanism fails to support recursion because:

    1. It stores only one return address per subroutine, overwriting the previous one on re-entry
    2. It uses too many registers
    3. It is slower than a stack-based call
    4. Recursion is a purely software concept unrelated to linkage mechanisms
    Show answer

    Answer: A — It stores only one return address per subroutine, overwriting the previous one on re-entry

    A recursive call re-enters the same subroutine before the outer call has returned, and BSA has only one slot to hold a return address — the second call's address overwrites the first, so the original return path is lost.

  7. Programmed I/O, compared to interrupt-driven I/O, is characterised by:

    1. The CPU busy-waiting in a polling loop, wasting cycles
    2. The device signalling the CPU only when ready, freeing the CPU meanwhile
    3. Direct memory access with no CPU involvement
    4. Never being used in any real system
    Show answer

    Answer: A — The CPU busy-waiting in a polling loop, wasting cycles

    Programmed I/O repeatedly polls a status flag before every word transfer, which is simple to implement but ties up the CPU the entire time — the opposite of interrupt-driven I/O, which lets the CPU do other work until signalled.

  8. Which of the following are logic (not arithmetic) microoperations? (More than one option may be correct.)

    1. Bitwise AND with a mask
    2. Bitwise XOR for selective complementing
    3. 2's-complement subtraction
    4. Increment by 1
    Show answer

    Answer: A — Bitwise AND with a mask; B — Bitwise XOR for selective complementing

    AND and XOR operate bit-independently with no carry propagation between bits, which is what makes them logic rather than arithmetic microoperations; subtraction and increment both involve carry propagation across bit positions, which is the arithmetic signature.

  9. An arithmetic right shift of the 8-bit signed (2's complement) value 11110000 (which represents −16) by one position gives the bit pattern _____ (write as 8 bits).

    Numerical answer — type the value.

    Show answer

    Answer: 11111000

    Arithmetic right shift preserves the sign bit by replicating it into the vacated most-significant position: shifting 11110000 right by one, keeping the leading 1, gives 11111000, which is −8 — correctly halving −16 towards negative infinity.