Sequential Circuits — Flip-Flops, Counters and Timing
A combinational circuit's output depends only on its present inputs; a sequential circuit's output depends on the inputs and on what happened before, which is to say it has state. That single addition changes what a question can ask. It can now ask what the circuit reaches after a number of clock edges, and it can ask how fast the clock may run — and the second kind is where marks are most reliably lost, because it is not about logic at all. The distinction to fix first is latch versus flip-flop: a latch is level-sensitive and follows its input for as long as it is enabled, while a flip-flop is edge-triggered and samples only at a clock edge. Almost every synchronous design uses flip-flops precisely so that state changes happen at one instant rather than throughout an interval. Of the four flip-flops, the D type is the one to think in — the others are conveniences built on it, and the excitation table for each is worth deriving rather than memorising: to make a JK go from 0 to 1 you need J = 1 and K = anything, which is what the don't-care entries in an excitation table mean. Two counting facts then cover a large share of the questions: a mod-N counter needs ⌈log₂N⌉ flip-flops, so mod-10 and mod-16 both need four and mod-60 needs six; and a ripple counter's delays accumulate while a synchronous counter's do not, which is the whole reason synchronous designs dominate despite costing more gates.
Counters: How Many Flip-Flops, and How Fast
| Counter | Flip-flops | Note |
|---|---|---|
| mod-8 | 3 | Exactly filled: 2³ = 8 |
| mod-10 (decade) | 4 | 2³ = 8 is too few; six states unused |
| mod-16 | 4 | Same count as mod-10 — the ceiling, not the value |
| mod-60 | 6 | 2⁵ = 32 too few, 2⁶ = 64 enough |
⚠️ A ripple counter is not a slow synchronous counter — it is a different circuit
In a ripple (asynchronous) counter each flip-flop clocks the next, so a 4-bit ripple counter built from flip-flops of 10 ns propagation delay takes up to 4 × 10 = 40 ns to settle, and during that window the outputs pass through states the count never actually visits — the source of decoding glitches. In a synchronous counter every flip-flop shares one clock, so the outputs change together and the delay does not accumulate; what limits the clock instead is one stage: the maximum frequency is 1 / (t_pd + t_comb + t_setup). With a 10 ns propagation delay, 8 ns of combinational logic between stages and a 5 ns setup requirement, that is 1 / 23 ns ≈ 43.5 MHz. Note what is not in that sum: the number of bits. Adding a fifth flip-flop to a synchronous counter does not slow it down, and adding one to a ripple counter does.A shift register is the other standard sequential block, and the questions on it are traces: n flip-flops in a chain move the data one position per clock, so a serial-in serial-out register of n stages delays a bit stream by exactly n clocks. Feed the output back through XOR taps and it becomes a ring or Johnson counter — a ring counter of n flip-flops has n states, a Johnson counter 2n, and confusing those two counts is the usual error.
Key takeaways
- A latch is level-sensitive; a flip-flop is edge-triggered and samples only at a clock edge.
- SR forbids S = R = 1; JK turns that case into a toggle; T is a JK with its inputs tied.
- An excitation table’s don’t-cares are design freedom, and they make JK counters cheaper than D counters.
- A mod-N counter needs ⌈log₂N⌉ flip-flops — mod-10 and mod-16 both need four.
- Ripple-counter delay is n × t_pd and grows with the bit count; a synchronous counter’s does not.
- Maximum synchronous clock = 1/(t_pd + t_comb + t_setup) — the word length does not appear in it.
- A ring counter of n flip-flops has n states; a Johnson counter of n has 2n.
Practice questions (8)
Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.
How many flip-flops are required to build a mod-60 counter?
Numerical answer — type the value.
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Answer: 6
The requirement is ⌈log₂N⌉: 2⁵ = 32 is fewer than 60, and 2⁶ = 64 is enough, so six flip-flops. Four of the 64 states go unused, which is normal and is what the counter’s reset logic exists to handle. The two errors worth naming are answering 5 by rounding the logarithm down, and answering 60 by reading "mod-60" as a count of cells rather than of states. Note also that mod-10 and mod-16 both need four — the ceiling depends on the power of two above N, not on N itself.A 4-bit ripple counter uses flip-flops with a propagation delay of 10 ns each. The worst-case time for the counter to settle after a clock edge is:
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Answer: B — 40 ns
In a ripple counter each flip-flop is clocked by the previous one’s output, so a change at the least significant bit must propagate through all four stages: 4 × 10 = 40 ns. Option A is the delay of a single stage, and is the answer for a synchronous counter of any width — which is the real content of the question, since the contrast is the reason both designs exist. During those 40 ns the outputs pass through intermediate patterns the count never truly occupies, and a decoder watching them will glitch; that is why ripple counters are not used where the outputs drive logic.A synchronous counter uses flip-flops with 10 ns propagation delay and 5 ns setup time, with 8 ns of combinational logic between stages. What is the maximum clock frequency in MHz? (Round to two decimals.)
Numerical answer — type the value.
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Answer: 43.48
One clock period must accommodate the flip-flop’s propagation delay, the combinational logic it feeds, and the setup time of the flip-flop that receives the result: 10 + 8 + 5 = 23 ns, so f(max) = 1/23 ns ≈ 43.48 MHz. What must not enter the sum is the number of stages — a synchronous counter’s stages all switch on the same edge, so widening it does not slow it. Leaving out the setup time gives 55.6 MHz and is the commonest error; leaving out the combinational delay gives 66.7 MHz and is the second. Hold time, by contrast, never appears in a maximum-frequency calculation: it constrains the minimum delay, and violating it cannot be fixed by slowing the clock.In a JK flip-flop, the input combination required to take the output from 0 to 1 is:
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Answer: B — J = 1, K = don’t care
From a present state of 0, J = 1 with K = 0 sets the output to 1, and J = 1 with K = 1 toggles it, which from 0 also gives 1. So J must be 1 and K is genuinely irrelevant: the excitation entry is J = 1, K = X. Option A is the characteristic-table answer — correct as one way to do it, but the question asks what is required, and requiring K = 0 throws away the freedom. That freedom is not cosmetic: each X becomes a don’t-care in the Karnaugh map for that input, which is exactly why JK-based counters need fewer gates than D-based ones.Which of the following distinguish a flip-flop from a latch? (More than one may be correct.)
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Answer: A — It changes state only at a clock edge; C — Its output cannot follow its input throughout an enable interval
A and C, which are one property stated twice. Edge-triggering is the definition: a flip-flop samples at the instant of a clock transition, so its output cannot track its input over a window (C follows from A). B is true of both and therefore distinguishes nothing — storing a bit is what they have in common, not what separates them. D is backwards: it is the latch that needs no clock, only an enable level, and a flip-flop that must be clocked. The practical consequence is why synchronous design exists at all — if state can only change at one instant, every timing question reduces to whether one clock period is long enough.A ring counter and a Johnson (twisted-ring) counter are each built from 4 flip-flops. Their numbers of distinct states are respectively:
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Answer: A — 4 and 8
A ring counter circulates a single 1 through n stages, so it has exactly n = 4 states. A Johnson counter feeds back the complement of the last output, which fills the register with 1s and then empties it, giving 2n = 8 states. Neither reaches 2⁴ = 16, and that is the point of both: they trade state count for decoding simplicity, since each state has a unique single-bit or single-transition signature and needs no full decoder. Option D is what you get by assuming four flip-flops must give sixteen states — true of a binary counter, false of both of these.Four D flip-flops are each wired with D = Q′ and cascaded, the output of one clocking the next. A 16 MHz signal drives the first. The output frequency of the fourth is:
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Answer: C — 1 MHz
With D = Q′ the flip-flop toggles on every clock edge, so its output completes one cycle per two input cycles — a divide-by-two. Four such stages in series divide by 2⁴ = 16, giving 16 MHz / 16 = 1 MHz. Option A is one stage and option B two, which is what a candidate answers by dividing by the number of stages rather than by two raised to it. This is also the ripple counter of the previous question seen from the other side: each stage is a divide-by-two, which is exactly why an n-stage ripple counter counts to 2ⁿ.In an SR latch built from NOR gates, applying S = R = 1 is forbidden because:
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Answer: B — Both outputs go to the same value, so they are no longer complementary
A NOR-based SR latch holds Q and Q′ as each other’s complement, and that invariant is what makes it a one-bit memory. With S = R = 1 both NOR gates are forced low, so Q = Q′ = 0 — the two outputs agree, which the rest of the circuit reading them is not built for. Worse, when the inputs are released the state the latch settles into depends on which gate happens to be faster, so the result is not merely invalid but unpredictable — a race condition. The JK flip-flop exists to convert this case into something useful: it makes S = R = 1 mean toggle. Option C describes a latch that has been set, which is normal operation, not the forbidden state.