Machine Instructions, Addressing Modes and the Data Path
Like Digital Logic, this is Section 3 of the Computer Science paper. Several other papers have architecture content of their own, with their own sub-lists, so if you sit one of those, read your own syllabus before assuming this section is yours. An instruction set is a contract: it fixes what the programmer may say and therefore what the hardware must be able to do, and every question in this chapter is about a consequence of that contract. Addressing modes are the part worth being exact about, because the exam asks how many memory accesses an instruction costs, and the answer is decided entirely by the mode. Immediate costs none beyond the fetch — the operand is in the instruction. Direct costs one. Indirect costs two, because the address must be fetched before the operand can be. Register costs none, register-indirect one. Indexed and base-plus-offset cost one, plus an addition the ALU does for free. Getting these counts right is worth more marks than knowing the names. The data path is then the hardware that makes an instruction happen — registers, ALU, buses — and the control unit is what drives it through the fetch–decode–execute sequence, in one of two ways whose trade-off is examinable: hardwired control is a fixed sequential circuit, fast and inflexible, while microprogrammed control stores the sequence as microinstructions in a control memory, slower and changeable without rewiring. The whole of RISC-versus-CISC follows from that choice: a small regular instruction set can be hardwired and pipelined, a large irregular one usually cannot.
The Data Path and Two Ways to Control It
Every instruction runs the same outer loop — fetch, decode, execute — and the data path is the hardware it runs on: a program counter, an instruction register, a register file, an ALU, and buses between them. What varies is how many clock cycles each step takes and how the steps are sequenced. A single-bus data path needs more cycles than a three-bus one because only one transfer can happen at a time, which is why "how many cycles does this instruction take" is answerable only once the bus structure is given.
| Aspect | Hardwired | Microprogrammed |
|---|---|---|
| What it is | A fixed sequential circuit | Microinstructions in a control memory |
| Speed | Faster — no control-memory read | Slower — each step is a memory read |
| Changing the instruction set | Requires redesigning the circuit | Rewrite the microcode — no rewiring |
| Suits | Small, regular sets — RISC | Large, irregular sets — CISC |
⚠️ RISC and CISC are not "fewer instructions" and "more instructions"
The count is a symptom, not the definition. What actually separates them is regularity: RISC instructions are fixed-length, mostly register-to-register, with memory touched only by explicit load and store instructions and every instruction taking a comparable number of cycles. That regularity is what makes hardwired control and deep pipelining possible, and the pipelining is where the performance comes from. CISC allows variable-length instructions and memory operands in arithmetic, which is convenient for a compiler writer and hostile to a pipeline, because the next instruction's length is not known until the current one is decoded. A question contrasting them is usually really asking which is easier to pipeline, and the answer follows from the regularity rather than from the number.Key takeaways
- Count memory accesses by addressing mode: immediate and register 0, direct and register-indirect 1, indirect 2.
- Indirect is the only mode with indirection in memory, so it is the one questions use to test counting.
- Total memory references include the instruction fetch — an indirect operand instruction costs three.
- PC-relative addressing is what makes code relocatable.
- Cycles per instruction depend on the bus structure — a single-bus data path needs more than a three-bus one.
- Hardwired control is faster and fixed; microprogrammed is slower and changeable without rewiring.
- RISC versus CISC is about regularity, not instruction count — regularity is what allows pipelining.
Practice questions (8)
Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.
An instruction ADD R1, @X uses indirect addressing for its second operand. Counting the instruction fetch, how many memory references does executing it require in total?
Numerical answer — type the value.
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Answer: 3
One reference fetches the instruction. Indirect addressing then needs two more: the first reads the address stored at X, and the second reads the operand from that address. Total three. The two wrong answers are both instructive — 2 forgets that indirection is a double dereference and treats @X like a direct operand, and 1 counts only the fetch. Register indirect would have given two in total, and that near-identical mode is what the question is really distinguishing.Which addressing mode requires no memory access beyond the instruction fetch?
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Answer: B — Immediate
In immediate mode the operand is a field of the instruction, so fetching the instruction has already fetched it — zero extra accesses. Register mode also costs zero, and is the other correct answer to this question when it is offered. Direct and indexed each cost one, and register indirect one. The pattern worth internalising is that a mode costs a memory access exactly when the operand lives in memory: immediate keeps it in the instruction, register keeps it in the register file, and everything else has to go and get it.Compared with hardwired control, microprogrammed control is:
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Answer: B — Slower and easier to modify
Microprogrammed control stores the control sequence as microinstructions in a control memory, so every step costs a control-memory read — that is the slowness — and changing the instruction set means rewriting microcode rather than redesigning a circuit, which is the flexibility. Hardwired control is the mirror image: a fixed sequential circuit, faster because there is nothing to read, and requiring a redesign to change. Option C is the answer a candidate gives by assuming the newer or more sophisticated technique must win on both axes; the whole point is that it is a trade, and it is the trade that decides which style of instruction set a machine can afford.Which of the following are characteristic of a RISC instruction set? (More than one may be correct.)
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Answer: A — Fixed-length instructions; C — Memory accessed only by explicit load and store instructions
A and C, and together they are what "regularity" means in practice. Fixed-length instructions let the next fetch begin before the current instruction is decoded, and confining memory traffic to load and store keeps every arithmetic instruction to a predictable number of cycles — both prerequisites for a deep pipeline. B is the CISC property: allowing an arithmetic instruction to reach into memory makes its latency unpredictable. D is also CISC-leaning; a small regular set is what makes hardwired control practical, and hardwired control is the faster of the two. Notice that "fewer instructions" appears nowhere in the answer — the count is a consequence, not the definition.A machine has 16-bit instructions, 8 addressing modes and 32 general-purpose registers. If an instruction has one register operand and one memory operand with a mode field, how many bits remain for the opcode?
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Answer: A — 3
32 registers need log₂32 = 5 bits; 8 addressing modes need log₂8 = 3 bits. With a 16-bit instruction and, for the memory operand, a 5-bit field of its own for the register the mode applies to, that is 5 + 3 + 5 = 13 bits of operand specification, leaving 16 − 13 = 3 bits for the opcode — enough for only eight instructions, which is exactly the pressure that pushes real machines to variable-length encodings. The arithmetic is easy and the marks are lost in the setup: every field is a log₂ of a count, so 32 registers is 5 bits and not 32, and 8 modes is 3 bits and not 8. Option B makes that second slip.PC-relative addressing is preferred for branch instructions mainly because:
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Answer: B — It makes the code relocatable
A PC-relative branch stores a displacement, not an absolute address, so the whole block of code can be loaded anywhere in memory and every branch inside it still lands correctly — that is relocatability, and it is what a loader and a shared library depend on. Option C is backwards: a displacement field is usually smaller than a full address, so the range is more limited, not larger — the limit is a real one and is why long jumps need a different mode. Option A is false, since the branch target instruction still has to be fetched.Auto-increment addressing is particularly suited to:
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Answer: B — Stepping through the elements of an array
Auto-increment uses the address in a register and then advances that register by the operand size, which is exactly the loop body of a sequential array traversal: fetch the element, move to the next, with no separate increment instruction. That saving of one instruction per iteration is the whole reason the mode exists. Option D is what immediate mode is for, and option A what direct mode is for. Auto-decrement, its mirror, is what a stack uses on push, which is the other place the mode earns its keep.A single-bus data path takes more clock cycles per instruction than a three-bus data path because:
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Answer: B — Only one register transfer can happen at a time
A bus can carry one value at a time, so a single-bus path must serialise the transfers an operation needs: getting both ALU operands in and the result out takes three separate cycles where a three-bus path does it in one. The extra cycles are a consequence of contention for the bus, not of a slower clock or slower ALU — the components are the same. This is why "how many cycles does this instruction take" is unanswerable until the bus structure is stated, and why questions in this section always state it.