A CMOS logic gate's very low static power draw is a direct consequence of

complementary pull-up and pull-down networks where exactly one conducts in any logic state

operating at a lower supply voltage than TTL always does

the absence of any capacitance in the circuit

The dual-slope (integrating) ADC's strong rejection of mains-frequency noise comes from

integrating over a fixed time set as a multiple of the mains period

using more comparators than a flash converter

its digital output being binary rather than Gray-coded

A flash ADC's defining tradeoff is that

it is the fastest architecture but its comparator count doubles for each extra bit of resolution

it is the slowest architecture but needs the fewest components

it is the fastest architecture but its comparator count doubles for each extra bit of resolution

it needs a DAC in its feedback loop

Effective number of bits (ENOB) of a real ADC

accounts for real noise and non-linearity, and is at or below the nominal bit count

always equals the nominal resolution printed on the datasheet

accounts for real noise and non-linearity, and is at or below the nominal bit count

can exceed the nominal bit count if the reference is very stable

is a property of the DAC in the feedback loop only

In virtual instrumentation, the front panel of knobs and dials is replaced by

software running on a general-purpose computer connected to the same DAQ hardware

a completely new set of physical hardware

software running on a general-purpose computer connected to the same DAQ hardware

a purely mechanical analog readout

Among the AI applications this syllabus names for instrumentation, sensor linearisation refers to

learning and correcting a sensor's non-linear response so the reported value is accurate

physically replacing a non-linear sensor with a linear one

learning and correcting a sensor's non-linear response so the reported value is accurate

increasing the sensor's supply voltage until its response becomes linear

a hardware filter placed before the ADC

Digital Logic, Data Converters and Embedded Systems

Section 7 of the GATE Instrumentation Engineering (IN) paper. A sensor's world is analog and continuous; everything downstream of this section — a microcontroller, a data-logger, an IoT node — is digital and discrete, and this section is the bridge between the two. Start with combinational logic (number systems, gate minimisation, multiplexers, IC families) and sequential logic (flip-flops, counters, finite state machines) as the vocabulary; then the analog front end and the converters — ADC and DAC — that are the literal crossing point between an analog voltage and a digital word, with the specifications that decide how faithfully that crossing is made; and finally the embedded systems and data-acquisition layer that reads the converter, runs the logic and reports the result — the layer where, increasingly, a small amount of on-board AI now does sensor linearisation and calibration that used to be a lookup table.

1. Number systems, combinational logic and IC families

Combinational logic has no memory: an output depends only on the present inputs. Boolean function minimisation (by Karnaugh map for a handful of variables, or the Quine-McCluskey method for more) reduces a truth table to the smallest sum-of-products or product-of-sums, which matters directly because fewer gates means less delay, less power and fewer places for a fault to hide. A multiplexer selects one of several data inputs onto a single output under the control of select lines; a demultiplexer does the reverse, routing one input to one of several outputs — and a sufficiently large multiplexer can implement any Boolean function of its select lines directly, without a separate gate network.

IC logic families, by what distinguishes each
Family	Built from	Known for
TTL	bipolar transistors	good speed, moderate power, older standard
CMOS	complementary MOSFETs	very low static power, high noise margin, now dominant
ECL	bipolar, non-saturating	the fastest of the three, at the highest power cost

🎯 Why CMOS displaced TTL almost everywhere

A CMOS gate is built from complementary pull-up (PMOS) and pull-down (NMOS) networks such that, in either logic state, exactly one network conducts and the other is off — so static (DC) current, and with it static power, is close to zero. TTL's bipolar structure has no such property, and always draws some standing current. That single fact is why battery-powered and high-density digital instrumentation is built in CMOS almost without exception today.

2. Sequential circuits and finite state machines

A sequential circuit's output depends on the present input AND the present state, stored in flip-flops. The SR latch is the primitive; the D flip-flop stores one bit exactly as presented at the clock edge (the workhorse of registers); the JK flip-flop resolves the SR latch's forbidden input case and can be wired to toggle; the T flip-flop toggles on every clock and is the natural building block of a binary counter. A shift register moves its stored bits one position per clock — serial-in-serial-out, serial-in-parallel-out, and the reverse pairs — and is the standard way to convert between serial and parallel data.

A Moore machine's output depends on the present state alone.
A Mealy machine's output depends on the present state AND the present input, so it can react within the same clock cycle.
A counter is the simplest finite state machine: its 'input' is just the clock, and its states are the count sequence itself.

🧠 Telling Moore and Mealy apart on a timing diagram

On a timing diagram, a Mealy output can change the instant an input changes, mid-cycle, because it is a direct function of that input; a Moore output only ever changes at a clock edge, because it is a function of the state register alone. If a diagram shows an output edge that lines up with an input edge rather than a clock edge, the machine is Mealy.

A monostable timer IC configured as a one-shot and a free-running astable timer are both standard building blocks for generating a delay or a clock, but a purpose-built counter — ripple (asynchronous, cheap, but with propagation delay accumulating stage to stage) or synchronous (all flip-flops clocked together, faster, more hardware) — is the usual choice when the count value itself, not just a delay, matters to the rest of the system.

3. Analog front end and data converters

The analog front end prepares a signal before it ever reaches a converter: an analog multiplexer shares one ADC among several channels; a programmable-gain amplifier scales each channel to use the converter's full range regardless of that channel's native signal level; a sample-and-hold circuit freezes the signal for the duration of the conversion, since most ADC architectures need a steady input while they work.

ADC architectures, told apart by their tradeoff
Type	Principle	Strength / weakness
Successive approximation (SAR)	binary search using a DAC in the loop	good speed-resolution balance, n clock cycles for n bits
Integrating (dual-slope)	integrate input then a reference, count the time ratio	excellent noise rejection, very slow
Flash	one comparator per code level, all at once	fastest possible, comparator count doubles per extra bit
Sigma-delta	oversampling plus noise shaping, then digital filtering	very high resolution, low bandwidth

🎯 Why an integrating ADC rejects noise so well

A dual-slope ADC integrates the unknown input over a FIXED time; if that fixed time is chosen as an exact multiple of the mains period (20 ms for 50 Hz), any mains-frequency interference riding on the signal integrates to exactly zero net contribution over that window. This is why bench multimeters and other precision, low-speed instruments favour this architecture despite its low speed — the noise rejection is a direct consequence of the timing choice, not an accident.

A DAC is judged by the same family of specifications as an ADC: resolution (the number of bits, setting the smallest representable step), quantisation error (at most half the least-significant-bit's step, an unavoidable rounding), dynamic range and ENOB (effective number of bits — the resolution the converter ACTUALLY delivers once real noise and non-linearity are accounted for, always at or below the nominal bit count), and settling/conversion time. INL and DNL describe how far actual code transitions deviate from ideal — DNL below -1 LSB means the converter can even be non-monotonic, missing a code outright.

4. Embedded systems, data acquisition and on-board AI

A microprocessor needs external memory and I/O built around it; a microcontroller integrates CPU, memory and I/O peripherals (timers, ADC, serial ports) on one chip, which is why almost every instrumentation node is built around a microcontroller rather than a bare microprocessor — fewer external parts, lower cost, lower power. Memory and I/O interfacing follows one of two schemes: memory-mapped I/O, where peripherals share the same address space as memory and are accessed with ordinary load/store instructions, or isolated (port-mapped) I/O, with its own address space and dedicated instructions — the tradeoff is address-space efficiency against instruction-set simplicity.

A data acquisition (DAQ) system is the whole chain end to end: sensor, signal conditioning, multiplexer, sample-and-hold, ADC, and a processor that reads, timestamps and stores or transmits the digitised value. Virtual instrumentation replaces a dedicated front panel of knobs and dials with software running on a general-purpose computer connected to that same DAQ hardware — the measurement hardware is real, the instrument's controls and displays are software. An IoT sensor node extends this one step further: local acquisition and light processing, then wireless transmission to a gateway or cloud service, usually under a tight power budget that shapes every other design choice in the node.

ℹ️ Where AI has actually entered this syllabus

The syllabus names three specific instrumentation tasks for basic AI, and it is worth being precise about which: sensor linearisation (learning a sensor's non-linear response so the reported value is corrected without a hand-fitted polynomial), system calibration and tuning (adjusting parameters from data rather than a fixed table), and signal classification (deciding which of several known categories a measured signal belongs to). This is pattern-fitting bolted onto an otherwise conventional instrumentation chain, not a different measurement principle.

⚠️ DNL below -1 LSB is not just 'less accurate'

Differential non-linearity measures the actual step size between adjacent codes against the ideal one LSB step. A DNL error more negative than -1 LSB means a code step that should have been positive is actually negative or zero — the converter can skip a code entirely, producing a genuinely non-monotonic transfer curve, which is a qualitatively different failure from ordinary reduced accuracy.

Key takeaways

CMOS's complementary pull-up/pull-down structure gives near-zero static power, which is why it displaced TTL almost everywhere digital instrumentation runs on batteries.
A Mealy output can change mid-cycle with the input; a Moore output only changes at a clock edge — read a timing diagram for which edge the output tracks.
An integrating (dual-slope) ADC rejects mains-frequency noise by integrating over a fixed time chosen as a multiple of the mains period — precision at the cost of speed.
ENOB is what a converter actually delivers once real noise and non-linearity are counted, always at or below the nominal bit count — never read the datasheet's bit count as the achieved resolution.
A DNL error worse than -1 LSB can make a converter skip a code entirely — a qualitatively different failure from ordinary reduced accuracy.
A microcontroller integrates CPU, memory and I/O on one chip, which is why it, not a bare microprocessor, is the default choice for an instrumentation node.

Practice questions (8)

Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.

A CMOS logic gate's very low static power draw is a direct consequence of
1. using only NMOS transistors
2. complementary pull-up and pull-down networks where exactly one conducts in any logic state
3. operating at a lower supply voltage than TTL always does
4. the absence of any capacitance in the circuit
Show answer
Answer: B — complementary pull-up and pull-down networks where exactly one conducts in any logic state
The complementary PMOS/NMOS structure means exactly one network conducts in each stable logic state, so almost no DC path exists from supply to ground — static power is near zero. This is a structural property, not simply a matter of a lower supply voltage, and it has nothing to do with the absence of NMOS or of capacitance (switching, dynamic power still exists because of capacitance).
A finite state machine whose output changes the instant an input changes, within the same clock cycle, is
1. a Moore machine
2. a Mealy machine
3. a ripple counter
4. a shift register
Show answer
Answer: B — a Mealy machine
A Mealy machine's output is a function of both the present state and the present input, so it can respond within the same cycle an input changes; a Moore machine's output depends on state alone and only ever updates at a clock edge. Ripple counters and shift registers are specific circuits, not a general answer to this classification.
The dual-slope (integrating) ADC's strong rejection of mains-frequency noise comes from
1. its very high sampling speed
2. integrating over a fixed time set as a multiple of the mains period
3. using more comparators than a flash converter
4. its digital output being binary rather than Gray-coded
Show answer
Answer: B — integrating over a fixed time set as a multiple of the mains period
Integrating over a fixed window that is an exact multiple of the mains period makes any mains-frequency interference average to zero net contribution over that window — this is a direct, deliberate consequence of the timing choice, and is exactly why this architecture is slow but very clean. It has nothing to do with comparator count or output coding.
A flash ADC's defining tradeoff is that
1. it is the slowest architecture but needs the fewest components
2. it is the fastest architecture but its comparator count doubles for each extra bit of resolution
3. it needs a DAC in its feedback loop
4. it has no quantisation error
Show answer
Answer: B — it is the fastest architecture but its comparator count doubles for each extra bit of resolution
A flash converter uses one comparator per quantisation level and decides all bits at once, making it the fastest architecture, but the comparator count is 2^n - 1 for n bits, so resolution is expensive to add. A DAC-in-the-loop describes SAR, not flash, and no ADC architecture is free of quantisation error.
Effective number of bits (ENOB) of a real ADC
1. always equals the nominal resolution printed on the datasheet
2. accounts for real noise and non-linearity, and is at or below the nominal bit count
3. can exceed the nominal bit count if the reference is very stable
4. is a property of the DAC in the feedback loop only
Show answer
Answer: B — accounts for real noise and non-linearity, and is at or below the nominal bit count
ENOB folds real-world noise and distortion into a single figure that is always at or below the datasheet's nominal bit count, never above it — the nominal count is an ideal ceiling, not a guarantee. It applies to the converter as measured, not to any one internal component alone.
The chief reason almost every instrumentation node is built around a microcontroller rather than a bare microprocessor is that
1. microcontrollers always run at higher clock speeds
2. a microcontroller integrates CPU, memory and I/O peripherals on one chip, needing fewer external parts
3. microprocessors cannot execute embedded software at all
4. microcontrollers do not need any power supply
Show answer
Answer: B — a microcontroller integrates CPU, memory and I/O peripherals on one chip, needing fewer external parts
The integration of CPU, memory and I/O on one chip is exactly what removes the need to design and populate a board with separate memory and peripheral chips, cutting cost, board area and power — the reason it dominates instrumentation nodes. Speed is not the deciding factor, microprocessors run embedded software perfectly well, and both need power.
In virtual instrumentation, the front panel of knobs and dials is replaced by
1. a completely new set of physical hardware
2. software running on a general-purpose computer connected to the same DAQ hardware
3. a purely mechanical analog readout
4. a second, redundant sensor
Show answer
Answer: B — software running on a general-purpose computer connected to the same DAQ hardware
Virtual instrumentation keeps the real measurement hardware (sensor through DAQ) and replaces only the controls and displays with software on a general-purpose computer — that is the whole idea, and it is why the same DAQ hardware can present as many different 'instruments' as there is software written for it.
Among the AI applications this syllabus names for instrumentation, sensor linearisation refers to
1. physically replacing a non-linear sensor with a linear one
2. learning and correcting a sensor's non-linear response so the reported value is accurate
3. increasing the sensor's supply voltage until its response becomes linear
4. a hardware filter placed before the ADC
Show answer
Answer: B — learning and correcting a sensor's non-linear response so the reported value is accurate
Sensor linearisation in this context is a software correction — learning the sensor's actual non-linear characteristic (in place of a hand-fitted polynomial or lookup table) and correcting the reported reading for it; it does not involve replacing the sensor, adjusting its supply, or an analog filter.