The Devices: P-N Junction, Zener, BJT, MOS Capacitor, MOSFET and Scaling, LED, Photodiode and Solar Cell
V_bi = (kT/q) ln(N_A N_D/n_i²), which is the price of lining up two Fermi levels, and the depletion width W, which is what Poisson's equation gives you once you know the charge. The chapter is worked around one reference junction — N_A = 10¹⁷ cm⁻³ on N_D = 10¹⁶ cm⁻³ in silicon at 300 K, with kT/q = 0.0259 V and n_i = 1.5 × 10¹⁰ cm⁻³ — and one reference MOS structure with a 10 nm oxide on a 10¹⁷ cm⁻³ substrate. Carry those two through, because almost every quantity in Section 3 of the GATE Electronics and Communication Engineering paper is a derivative of them.The Biased Diode, Breakdown, and the Zener Regulator
Forward bias lowers the barrier by V, so the minority-carrier concentration injected at each depletion edge is multiplied by exp(V/V_T). Solving the minority-carrier diffusion equation from the previous chapter in each quasi-neutral region and adding the two diffusion currents gives the ideal diode equation I = I_S (exp(V/nV_T) − 1), with I_S = qA(D_p p_n0/L_p + D_n n_p0/L_n). Three readings of that equation matter more than the derivation. First, I_S contains the minority-carrier equilibrium concentrations, so it is proportional to n_i² — which means I_S varies as exp(−E_g/kT) and rises by roughly an order of magnitude for every 15 °C in silicon. Second, in reverse bias the exponential dies and I → −I_S, a current independent of voltage, which is what makes a reverse-biased junction a current source rather than a resistor. Third, the ideality factor n is 1 when diffusion dominates and tends toward 2 when recombination inside the depletion region dominates, which is the low-current regime. Practically, at fixed current the forward voltage falls by about 2 mV/°C, and a decade of current change costs 2.303 × 25.9 = 59.6 mV — the '60 mV per decade' every analogue designer quotes.
For small-signal work the diode is a resistance in parallel with two capacitances. The dynamic resistance is r_d = dV/dI = nV_T/I, so at I = 1 mA and n = 1, r_d = 0.0259/10⁻³ = 25.9 Ω — a number worth memorising, because it makes r_d ≈ 26/I(mA) Ω a one-second calculation. The junction (depletion) capacitance C_j = ε_s A/W dominates in reverse bias, falls as (V_bi + V_R)^(−1/2) for an abrupt junction, and is what a varactor exploits. The diffusion (storage) capacitance C_d = τ I/V_T dominates in forward bias and represents the charge stored in the quasi-neutral regions rather than any geometric separation; it is proportional to current, so it is enormous in a forward-biased diode and is why a diode does not switch off instantly. That stored charge has to be removed before the junction can support reverse voltage, which is the reverse recovery time — and, as the previous chapter noted, why fast diodes are deliberately lifetime-killed with gold or platinum. Beyond a critical reverse voltage the junction breaks down by one of two distinct mechanisms, and the syllabus names the diode built to exploit them.
| Feature | Zener (tunnelling) breakdown | Avalanche (multiplication) breakdown |
|---|---|---|
| Mechanism | Valence electrons tunnel straight into the conduction band across a very narrow barrier | A carrier gains enough energy to ionise a lattice atom; the products do the same |
| Needs | Heavy doping on both sides, so W is only nanometres | A wide depletion region for the carrier to accelerate in |
| Typical breakdown voltage | Below about 5 V | Above about 7 V |
| Temperature coefficient | Negative — a hotter lattice narrows E_g, easing tunnelling | Positive — more phonons means more scattering before ionisation |
| Between 5 and 7 V | Both act together; the two coefficients cancel | This is why precision references are 5.6 to 6.2 V |
15 V supply, a series resistor R_S = 220 Ω, a 6.2 V Zener across the output, and a load R_L = 1 kΩ. The load draws I_L = 6.2/1000 = 6.2 mA. The series resistor passes I_S = (15 − 6.2)/220 = 8.8/220 = 40 mA. The Zener therefore takes the difference, I_Z = 40 − 6.2 = 33.8 mA, and dissipates 6.2 × 33.8 = 210 mW. So far, so ordinary. Now ask the question the datasheet is really about: what is the worst case? It is not full load. Disconnect the load entirely and the series resistor still passes 40 mA — it only sees the supply and the Zener voltage — but now all of it goes through the diode: I_Z = 40 mA and P_Z = 6.2 × 40 = 248 mW. A 250 mW Zener, which looked to have 40 mW of headroom at full load, is at 99 per cent of its rating with the load removed, and one more volt of supply tolerance destroys it. The worst-case dissipation in a shunt regulator is at maximum input and no load, and that is the calculation the part is chosen against — here a 400 mW or 500 mW device. The other end of the range has a rule too: regulation collapses when I_Z falls below the knee, perhaps 5 mA, so the maximum load current is 40 − 5 = 35 mA and the minimum load resistance is 6.2/0.035 = 177 Ω. Between those two limits it works. Finally the figure of merit: with a Zener dynamic resistance r_z = 5 Ω, the fraction of input ripple reaching the output is r_z/(R_S + r_z) = 5/225 = 0.0222, that is 22 mV of output change per volt of input change — good, but not the perfect source the ideal-diode symbol suggests.The BJT: Two Junctions, One Thin Base, and Why `β` Is So Fragile
A bipolar junction transistor is an emitter, a base and a collector — n-p-n or p-n-p — and the whole trick is geometric. Forward-bias the emitter-base junction and the emitter injects a large minority-carrier population into the base. Reverse-bias the base-collector junction so its field sweeps up anything that reaches it. Now make the base much thinner than the minority-carrier diffusion length: for a base 0.5 µm wide against the 45.5 µm electron diffusion length computed in the last chapter, the ratio is ninety to one, so almost every injected electron crosses the base by diffusion and is collected rather than recombining. I_C is therefore controlled by the emitter-base voltage and is nearly independent of V_CB — a current-controlled current source, and, crucially, the output current is set by the input junction, which is what makes it an amplifier. The two figures of merit are the common-base gain α = I_C/I_E and the common-emitter gain β = I_C/I_B, related by β = α/(1 − α) and α = β/(1 + β). The four operating modes follow from the two junction biases: both forward is saturation, both reverse is cut-off, emitter forward with collector reverse is the active region, and the reverse of that is reverse-active, which has a wretched gain because the collector was never designed to be an emitter.
β = α/(1 − α) and look at the denominator. At β = 100, α = 100/101 = 0.9901. Now improve the transistor very slightly, so that α = 0.995 — an absolute change of half a percentage point, a relative change of about 0.5 per cent. Then β = 0.995/0.005 = 199. β has doubled. The reason is structural: α is a number just below one, so 1 − α is a small difference of two nearly equal numbers, and β is one divided by that difference. Any quantity defined as the reciprocal of a small difference is fragile, and β is exactly that. Physically, α is set by two efficiencies multiplied together — the fraction of emitter current that is the desired carrier type (emitter injection efficiency, which needs the emitter doped far more heavily than the base) and the fraction of those carriers that survive the base (base transport factor, which needs the base thin). Both are process-dependent, both vary with temperature, and both vary from one device to the next on the same wafer, so β is routinely specified with a three-to-one spread — a part quoted as β = 100 may be anything from 60 to 300. The design consequence is the whole reason the next chapter's biasing section exists: a bias network whose collector current is proportional to β is not a design, it is a lottery. The same fragility shows up in leakage: I_CEO = (1 + β)I_CBO, so a 10 nA collector-base leakage becomes a 1.01 µA collector-emitter leakage at β = 100, amplified by the very mechanism that amplifies the signal.Three second-order effects turn the ideal current source into a real device, and all three come from the base. Base-width modulation, the Early effect: raising V_CE widens the base-collector depletion region, which eats into the base from the collector side, shortens the effective base width W_B, steepens the minority-carrier gradient across it and so raises I_C. That gives the active-region characteristics a finite slope, described by an Early voltage V_A — the extrapolated intercept on the V_CE axis — and an output resistance r_o = V_A/I_C. With V_A = 50 V and I_C = 1 mA, r_o = 50 kΩ, so raising V_CE from 2 V to 10 V raises I_C by 8/50 = 16 per cent. Punch-through: push V_CE far enough and the collector depletion region reaches all the way across to the emitter, W_B → 0, and the transistor is simply a short. High-current fall-off: at large I_C the injected minority density in the base rivals the base doping, high-level injection sets in, and β falls — which is why a transistor's β peaks at some mid-range current and droops at both ends. Small-signal, the BJT is characterised by g_m = I_C/V_T, which at 1 mA is 10⁻³/0.0259 = 38.6 mA/V, and r_π = β/g_m = 2.59 kΩ at β = 100. Note the beautiful consequence: the intrinsic gain g_m r_o = (I_C/V_T)(V_A/I_C) = V_A/V_T = 50/0.0259 = 1930, entirely independent of bias current.
Speed in a BJT is set by how long a carrier takes to cross the base. Diffusion across a base of width W_B takes a forward transit time τ_F = W_B²/2D_n, and for W_B = 0.5 µm = 5 × 10⁻⁵ cm with D_n = 20.7 cm²/s that is (5 × 10⁻⁵)²/(2 × 20.7) = 6.03 × 10⁻¹¹ s = 60.3 ps. The corresponding unity-gain frequency is f_T ≈ 1/2πτ_F = 2.64 GHz, and the frequency at which β itself has fallen to one is f_β = f_T/β = 26.4 MHz. The quadratic in W_B is the design lesson: halving the base width quarters the transit time, which is why the entire history of bipolar technology is a history of thinner bases, and why the heterojunction bipolar transistor — which uses a wide-gap emitter to get injection efficiency without needing a lightly doped base — can dope the base heavily, make it very thin, and reach hundreds of gigahertz. The same base thinness, of course, is what brings punch-through closer, so the base doping cannot be reduced to compensate. Every bipolar design is that trade: gain wants a thin lightly doped base, breakdown wants a thick heavily doped one.
The MOS Capacitor: Accumulation, Depletion, Inversion, and the Threshold Voltage Computed
A MOS capacitor is a metal or polysilicon gate, a thin oxide, and a semiconductor substrate — an ordinary capacitor except that one of its plates is a semiconductor and can therefore respond in more than one way. Take a p-type substrate at N_A = 10¹⁷ cm⁻³ under a 10 nm oxide. The oxide capacitance per unit area is C_ox = ε_ox/t_ox = 3.9 × 8.854 × 10⁻¹⁴/10⁻⁶ = 3.453 × 10⁻⁷ F/cm², which is 3.45 fF/µm² in the units a layout engineer uses. Now sweep the gate voltage and three regimes appear in order. Make the gate negative and holes — the majority carriers — are attracted to the surface: accumulation, a thin sheet of mobile charge right at the oxide, so the structure is a plain parallel-plate capacitor of value C_ox. Make the gate slightly positive and holes are pushed away, leaving behind immobile negative acceptor ions: depletion, and the capacitance is now C_ox in series with a depletion capacitance ε_s/W_d that shrinks as W_d grows, so the total falls. Push further and the surface potential bends the bands so far that the surface becomes n-type: inversion, a mobile electron sheet at the surface in a substrate that is doped p-type.
Strong inversion is conventionally defined as the point where the surface electron concentration equals the bulk hole concentration, which happens when the surface potential reaches 2φ_F, where φ_F = V_T ln(N_A/n_i) is how far the bulk Fermi level sits from the intrinsic level. For our substrate, φ_F = 0.0259 × ln(10¹⁷/1.5 × 10¹⁰) = 0.407 V — the identical number computed in the last chapter, because it is the identical quantity — so strong inversion needs a surface potential of 2φ_F = 0.814 V. Getting there costs three things, and the threshold voltage is their sum: V_T = V_FB + 2φ_F + Q_dep/C_ox. The flat-band voltage V_FB pays off the work-function difference between gate and substrate plus any fixed oxide charge, and for an n+ polysilicon gate on this substrate it is about −0.9 V. The 2φ_F bends the bands. And Q_dep/C_ox is the gate voltage dropped across the oxide holding up the depletion charge, where Q_dep = √(2qε_s N_A × 2φ_F) = √(2 × 1.6 × 10⁻¹⁹ × 1.036 × 10⁻¹² × 10¹⁷ × 0.814) = 1.643 × 10⁻⁷ C/cm², giving Q_dep/C_ox = 1.643 × 10⁻⁷/3.453 × 10⁻⁷ = 0.476 V. Adding up: V_T = −0.9 + 0.814 + 0.476 = 0.390 V. Cross-check the depletion charge against the geometry: W_dmax = √(2ε_s × 2φ_F/qN_A) = 1.027 × 10⁻⁵ cm = 103 nm, and qN_A W_dmax = 1.643 × 10⁻⁷ C/cm² ✓, the same number by a different route.
W_d freezes at W_dmax = 103 nm. What the capacitance then does depends entirely on how fast you measure it, and this is the part that confuses people. At low frequency the inversion electrons can be generated and recombined fast enough to follow the gate, so they act as the second plate and C climbs back to C_ox. At high frequency — a megahertz, say — they cannot: in a MOS capacitor the only source of inversion electrons is thermal generation in the depleted silicon, which is slow, so the inversion layer does not respond and the measured capacitance stays at the series combination of C_ox with ε_s/W_dmax. Compute it: ε_s/W_dmax = 1.036 × 10⁻¹²/1.027 × 10⁻⁵ = 1.009 × 10⁻⁷ F/cm², and in series with C_ox = 3.453 × 10⁻⁷ gives C_min = 7.81 × 10⁻⁸ F/cm², that is C_min/C_ox = 0.226. So the high-frequency C-V curve of a MOS capacitor falls from C_ox in accumulation to 22.6 per cent of C_ox in inversion, and the shape of that dip is the standard measurement from which t_ox, N_A and V_FB are extracted. Now add a source and a drain and the whole effect disappears. A MOSFET's inversion layer is connected to two heavily doped n+ regions that can supply and remove electrons in picoseconds, so the channel follows the gate at any frequency and the gate capacitance in inversion is C_ox, full stop. This is the single most important difference between the capacitor and the transistor, and it is why the deep-depletion curve you get by ramping a MOS capacitor's gate too fast is a diagnostic in the lab and an irrelevance in a circuit.The MOSFET: Triode, Saturation, Body Effect and Subthreshold
Add an n+ source and an n+ drain to the MOS capacitor and the inversion layer becomes a channel with somewhere to go. Above threshold the mobile sheet charge at a point in the channel is Q_n = C_ox(V_GS − V_T − V(x)), and integrating the drift current along the channel gives the triode (linear) expression I_D = µ_n C_ox (W/L)[(V_GS − V_T)V_DS − V_DS²/2]. Raise V_DS and the channel charge at the drain end shrinks until, at V_DS = V_GS − V_T, it reaches zero — the channel pinches off, and beyond that point further V_DS is absorbed in the small depleted region near the drain rather than changing the channel. So in saturation the current stops growing: I_D = ½ µ_n C_ox (W/L)(V_GS − V_T)². Work the reference device: t_ox = 10 nm gives C_ox = 3.453 × 10⁻⁷ F/cm², take the surface mobility µ_n = 400 cm²/V·s (roughly half the bulk value, because carriers in a channel are scattered by the oxide interface), so µ_n C_ox = 138 µA/V². With W/L = 10, V_GS = 1.2 V and the V_T = 0.390 V computed above, the overdrive is V_ov = 0.810 V and I_D = ½ × 138 × 10⁻⁶ × 10 × 0.810² = 454 µA. The transconductance is g_m = µ_n C_ox (W/L)V_ov = 1.12 mA/V, and the cross-check g_m = 2I_D/V_ov = 2 × 454 × 10⁻⁶/0.810 = 1.12 mA/V ✓.
Quantity at I = 454 µA | MOSFET (V_ov = 0.810 V) | BJT (V_A = 50 V) | Reading |
|---|---|---|---|
g_m | 1.12 mA/V | 17.5 mA/V | The BJT gives 15.6 times more transconductance for the same current |
g_m/I_D | 2/V_ov = 2.47 V⁻¹ | 1/V_T = 38.6 V⁻¹ | The BJT's exponential beats the MOSFET's square law |
Scaling of g_m with current | ∝ √I_D — quadruple g_m needs 16× current | ∝ I_C — linear | This is why low-power analogue still uses bipolar input stages |
Output resistance r_o | 1/λI_D = 44.1 kΩ at λ = 0.05 V⁻¹ | V_A/I_C = 110 kΩ | Both fall as 1/I |
Intrinsic gain g_m r_o | 49 V/V | 1930 V/V | V_A/V_T for the BJT — independent of current |
| Input resistance at the gate/base | Effectively infinite | r_π = β/g_m = 5.7 kΩ | The MOSFET's one decisive advantage |
Three departures from the square law are examinable in their own right. Channel-length modulation is the MOSFET's Early effect: beyond pinch-off the depleted region near the drain grows with V_DS, shortening the effective channel, so I_D = ½µ_nC_ox(W/L)V_ov²(1 + λV_DS) and the output resistance is r_o = 1/λI_D. At λ = 0.05 V⁻¹ and I_D = 454 µA that is 44.1 kΩ, giving an intrinsic gain g_m r_o = 49 — forty times worse than the bipolar figure, and the reason analogue MOS design leans so heavily on cascoding. Body effect: the threshold voltage is not a constant of the device but a function of the source-to-body voltage, V_T = V_T0 + γ(√(2φ_F + V_SB) − √(2φ_F)), with γ = √(2qε_sN_A)/C_ox = 0.527 V^½ for our device. Put just V_SB = 1 V on the body and ΔV_T = 0.527 × (√1.814 − √0.814) = 0.527 × (1.347 − 0.902) = 0.234 V, so V_T rises from 0.390 V to 0.624 V, a 60 per cent increase. That is why a stack of series transistors in a CMOS gate does not switch at the voltage the bottom one does, and why the source of an analogue device is tied to its own body wherever the layout permits.
I_D = 0 for V_GS < V_T, and every digital designer would love that to be true. It is not. Below threshold the surface is in weak inversion and the drain current is carried by diffusion, exactly like a bipolar transistor's, so it falls exponentially rather than stopping: I_D ∝ exp(qV_GS/nkT). The steepness of that fall is the subthreshold slope, and the best it can ever be is 2.303 kT/q = 59.6 mV per decade at 300 K — and with the body factor n = 1 + C_dep/C_ox, typically 1.3 to 1.5, a real device needs 80 to 90 mV to cut its current by a factor of ten. Now the consequence, which is the single most important fact in modern device engineering. kT/q is fixed by temperature and cannot be scaled. So if the supply voltage is reduced and V_T is reduced with it to preserve the overdrive, the off-state current rises by a factor of ten for every 90 mV that V_T comes down. A billion-transistor chip with 90 mV less threshold than it should have leaks ten times as much standing current, and leakage does not switch off between clock edges. This is why threshold voltages stopped scaling around 0.3 to 0.4 V, why supply voltages stalled near 1 V, and why every low-power technique in a modern chip — power gating, multiple thresholds, back-biasing — exists to work around one thermodynamic constant. It is also worth noting the temperature term: since the slope is proportional to T, subthreshold leakage worsens sharply when a chip heats up, which couples power to temperature and can run away.Scaling in MOSFETs: What Dennard Promised and What Actually Happened
Constant-field (Dennard) scaling is a recipe with one instruction: divide every length and every voltage by the same factor S, and multiply the doping by S. Do that and the electric field inside the device is unchanged, so the physics that could break — breakdown, velocity saturation, oxide reliability — does not get worse. Every other quantity then follows by algebra, and the algebra is worth doing once rather than memorising, because the exam asks for individual entries. Oxide thickness t_ox divides by S, so C_ox per unit area multiplies by S, but the gate area divides by S², so the gate capacitance divides by S. Current I ∝ (W/L)µC_ox V² scales as (1)(S)(1/S²) = 1/S, so current divides by S. Delay CV/I scales as (1/S)(1/S)/(1/S) = 1/S, so circuits get faster by S. Power VI scales as (1/S)(1/S) = 1/S², and since area also divides by S², power density is constant — which is the whole point, and the promise that let the industry double transistor count every couple of years while keeping the same package and the same fan.
| Quantity | Scales as | At S = 2 |
|---|---|---|
L, W, t_ox, junction depth | 1/S | × 0.5 — halved |
| Supply and threshold voltage | 1/S | × 0.5 — halved |
| Doping concentration | S | × 2 — doubled |
| Electric field | 1 — unchanged, by construction | × 1 — unchanged |
Gate capacitance C_ox W L | 1/S | × 0.5 — halved |
| Drain current | 1/S | × 0.5 — halved |
Gate delay CV/I | 1/S | × 0.5 — twice as fast |
Power per device VI | 1/S² | × 0.25 — quartered |
| Device density | S² | × 4 — quadrupled |
| Power density | 1 — flat | × 1 — the whole promise |
Switching energy CV² | 1/S³ | × 0.125 — an eighth |
59.6 mV/decade set by kT/q, and every 90 mV of threshold reduction multiplies static leakage by ten. So the supply voltage could not come down either, because a supply too close to the threshold leaves no overdrive and destroys the speed the scaling was for. Both stalled near 1 V and 0.3 V respectively in the mid-2000s. Look at what that does to the table: if V stays constant while lengths divide by S, then the field rises by S, the power per device divides only by S rather than S², and power density rises as S instead of staying flat. That is precisely the wall the industry hit — clock frequencies stopped climbing around 3 to 4 GHz not because transistors got slower but because the heat could not be removed — and the response was to stop scaling frequency and start scaling cores. A second set of failures arrived at the same time, all of them short-channel effects that the constant-field recipe assumes away: the drain's depletion region begins to control charge the gate is supposed to own, so V_T falls as L shrinks (V_T roll-off) and falls further as V_DS rises (drain-induced barrier lowering); the channel field exceeds 10⁴ V/cm everywhere, so carriers travel at v_sat and I_D becomes roughly linear in overdrive rather than quadratic; hot carriers injected into the oxide shift V_T over the product's life; and below about 1.2 nm of SiO₂ electrons tunnel straight through the gate, which is why high-permittivity dielectrics with metal gates replaced silicon dioxide — a physically thicker layer with the same electrical C_ox, quoted as an equivalent oxide thickness. The lesson to carry is not the table. It is that a scaling law is a set of assumptions, and the assumptions fail one at a time in a predictable order.LED, Photodiode and Solar Cell: One Junction, Three Quadrants
An LED is a forward-biased junction in a direct-gap material, arranged so that injected carriers recombine radiatively. The photon energy comes out at roughly the band gap, so the emitted wavelength is fixed by the material through λ(nm) = 1240/E_g(eV) — a relation worth deriving once from E = hc/λ and then using without thought. Gallium arsenide at E_g = 1.42 eV emits at 1240/1.42 = 873 nm, in the near infrared, which is exactly what a remote control and a short-haul fibre link want. To get visible red at 650 nm the gap must be 1240/650 = 1.91 eV, reached by alloying — aluminium gallium arsenide or gallium arsenide phosphide. Blue at 450 nm needs 1240/450 = 2.76 eV, which is why blue and white LEDs are indium gallium nitride: gallium nitride's own 3.4 eV gap would emit at 365 nm, in the ultraviolet, so indium is added to bring the gap down. And silicon, at 1.12 eV, would emit at 1107 nm if it emitted at all — which, being indirect, it effectively does not. The efficiency figures worth knowing are the internal quantum efficiency (photons generated per injected carrier pair), the extraction efficiency (photons that escape rather than being reabsorbed or totally internally reflected at the high-index semiconductor surface), and the product, the external quantum efficiency.
A photodiode runs the same junction backwards: reverse-bias it so its depletion region is wide and its field strong, let photons of energy above the gap create electron-hole pairs inside that region, and the field separates them before they can recombine, delivering a photocurrent proportional to the optical power. The figure of merit is the responsivity R = ηqλ/hc, which in practical units is R = ηλ(µm)/1.24 A/W. For a silicon photodiode with quantum efficiency η = 0.8 at λ = 0.85 µm, R = 0.8 × 0.85/1.24 = 0.548 A/W, so 10 µW of incident light gives 0.548 × 10 = 5.48 µA of photocurrent. Check that by counting photons: at 850 nm each photon carries 1240/850 = 1.459 eV = 2.337 × 10⁻¹⁹ J, so 10 µW is 10⁻⁵/2.337 × 10⁻¹⁹ = 4.28 × 10¹³ photons per second; at 80 per cent efficiency that is 3.42 × 10¹³ electrons per second, or 3.42 × 10¹³ × 1.6 × 10⁻¹⁹ = 5.48 µA ✓. Note what responsivity does with wavelength: it rises linearly with λ, because a longer-wavelength photon carries less energy so the same optical power delivers more photons — and then it collapses to zero past the cutoff wavelength λ_c = 1.24/E_g, which for silicon is 1.107 µm. That single number is why silicon photodiodes are useless at the 1.31 and 1.55 µm wavelengths that optical fibre actually uses, and why those receivers are germanium (λ_c = 1.88 µm) or indium gallium arsenide (λ_c ≈ 1.65 µm).
| Aspect | LED | Photodiode | Solar cell |
|---|---|---|---|
| Bias | Forward, tens of mA | Reverse (or zero for photovoltaic mode) | None — the cell is the source |
Operating quadrant of the I-V plane | First — consumes power | Third — consumes power | Fourth — delivers power |
| Material must be | Direct gap — GaAs, InGaN | Anything with E_g < hc/λ | Anything; Si dominates on cost |
| Key figure of merit | External quantum efficiency | Responsivity 0.548 A/W at 850 nm | Fill factor and efficiency |
| Wide gap is | Needed for short wavelengths | A liability — raises the cutoff | A trade: more V_oc, fewer photons absorbed |
| Speed is limited by | Carrier lifetime and junction capacitance | Transit time across the depletion region and RC | Irrelevant — a DC source |
I = I_L − I_S(exp(V/V_T) − 1), sitting in the fourth quadrant where V is positive and I negative — it is delivering power. Two limits define it. Short the terminals and V = 0, so I_sc = I_L: the short-circuit current is the photocurrent, and it is directly proportional to illumination. Open the terminals and I = 0, so V_oc = V_T ln(I_L/I_S + 1). Take a 10 cm × 10 cm silicon cell with a short-circuit current density of 35 mA/cm², giving I_sc = 3.5 A, and a reverse saturation current I_S = 3.5 × 10⁻¹⁰ A. Then V_oc = 0.0259 × ln(10¹⁰) = 0.0259 × 23.03 = 0.596 V. Neither of those extremes delivers any power — one has no voltage, the other no current — so the operating point is the knee in between, and the fill factor FF = P_max/(V_oc I_sc) measures how square the corner is; a good silicon cell reaches 0.80. So P_max = 0.80 × 0.596 × 3.5 = 1.67 W. Under the standard 1000 W/m² = 0.1 W/cm² test illumination the cell receives 100 × 0.1 = 10 W, so the efficiency is 1.67/10 = 16.7 per cent. Now the asymmetry that decides how these devices are used. Double the illumination: I_sc doubles, straightforwardly, to 7.0 A. But V_oc only rises by V_T ln 2 = 18 mV, from 0.596 to 0.614 V, because it depends on the logarithm of the photocurrent. Current is linear in light, voltage is logarithmic in it — which is why concentrating sunlight onto a small cell is a viable way to reduce cost per watt (the power scales almost with the concentration), why the same fact makes a photodiode's photovoltaic mode useful for measuring light over decades of intensity, and why a solar cell's output voltage is essentially a material property while its current is essentially an area-and-illumination property. It is also the deeper reason the band gap cannot be optimised freely: a wider gap raises V_oc but pushes λ_c down and throws away the long-wavelength half of the spectrum, and the optimum for the solar spectrum lands in the 1.1 to 1.4 eV window that silicon and gallium arsenide happen to occupy.Two refinements of the photodiode complete the syllabus's list. The PIN photodiode inserts a lightly doped, nearly intrinsic layer between the p+ and n+ regions, which does two things at once: it makes the depletion region wide, so more of the incident light is absorbed inside the field where the carriers will be collected rather than outside it where they must diffuse in slowly; and it lowers the junction capacitance, since C_j = ε_s A/W and W is now the whole intrinsic layer. Both improve speed, and the width is chosen as a trade between absorption (which wants it thick) and transit time (which wants it thin). The avalanche photodiode biases the junction just below breakdown so that each photogenerated carrier triggers impact ionisation and is multiplied by a factor M of ten to a hundred before it reaches the terminal, giving internal gain and an effective responsivity M × R. The catch is that multiplication is a statistical process, so it amplifies the noise as well as the signal and adds an excess noise factor of its own; an avalanche photodiode wins only when the following amplifier's noise, not the photodiode's, is the limit. Both devices also make the point the section began with: nothing new has been introduced. A PIN diode is a junction whose depletion width was chosen deliberately, and an avalanche photodiode is a junction biased into the regime the Zener section already described.
Key takeaways
V_bi = (kT/q)ln(N_A N_D/n_i²)is the price of aligning two Fermi levels: 0.754 V for10¹⁷on10¹⁶ cm⁻³. Poisson then givesW = 0.328 µm, of which 91 per cent sits on the lightly doped side — the asymmetry behind one-sided junctions, breakdown ratings and PIN diodes. CheckE_maxtwice, from the charge and from2V/W; both give4.60 × 10⁴ V/cm.- Zener breakdown is tunnelling (below ~5 V, negative temperature coefficient) and avalanche is multiplication (above ~7 V, positive), which is why 5.6–6.2 V references are the stable ones. In a shunt regulator the worst-case Zener dissipation is at no load: the 6.2 V part above sits at 210 mW loaded and 248 mW unloaded.
- A BJT works because its base is thin against the diffusion length — 0.5 µm against 45.5 µm. But
β = α/(1−α)is the reciprocal of a small difference, soαmoving from 0.990 to 0.995 takesβfrom 99 to 199. Never design to a value ofβ.g_m r_o = V_A/V_T =1930 independent of current, andτ_F = W_B²/2D_n =60.3 ps givesf_T =2.64 GHz. V_T = V_FB + 2φ_F + Q_dep/C_ox, and for a 10 nm oxide on10¹⁷ cm⁻³withV_FB = −0.9 Vthat is−0.9 + 0.814 + 0.476 =0.390 V. Body bias is not a second-order effect: just 1 V ofV_SBadds 0.234 V, a 60 per cent rise. The high-frequencyC-Vof the capacitor dips to 22.6 per cent ofC_ox; the transistor's does not, because its source supplies the inversion charge.- At the same 454 µA the MOSFET gives
g_m = 1.12 mA/Vand the BJT 17.5 mA/V, becauseg_m/I_Dis2/V_ovfor one and1/V_Tfor the other. MOSFETg_m ∝ √I_D, so quadrupling it costs sixteen times the current. Below thresholdI_Dis exponential with a floor of 59.6 mV/decade, and that floor is whyV_Tand the supply stopped scaling. - Constant-field scaling by
Sdivides length, voltage, current, capacitance and delay byS, multiplies doping and density, and keeps power density constant. It broke whenV_TandV_DDstopped scaling, after which power density rose asS— plus short-channel effects:V_Troll-off, DIBL, velocity saturation, hot carriers and gate tunnelling below ~1.2 nm of oxide. λ(nm) = 1240/E_g(eV)runs both ways: GaAs emits at 873 nm, red needs 1.91 eV, blue 2.76 eV, and silicon's cutoff at 1.107 µm is why fibre receivers are not silicon. Responsivity= ηλ/1.24 =0.548 A/W at 850 nm withη = 0.8. A solar cell'sI_scis linear in illumination whileV_ocis logarithmic — 18 mV per doubling — which is what makes concentration worthwhile.
Practice questions (8)
Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.
An abrupt silicon junction is heavily doped on the p side and carries 2 x 10^16 cm^-3 of donors on the n side, and its built-in potential is 0.80 V. Take the permittivity of silicon as 1.04 x 10^-12 F/cm, q = 1.6 x 10^-19 C, and the field at which silicon avalanches as about 3 x 10^5 V/cm. What is the peak field at zero bias, and how close is the junction to breakdown?
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Answer: A — 7.0 x 10^4 V/cm, comfortably below the avalanche field
Because one side is heavily doped the depletion region sits almost entirely in the lightly doped side, so the width follows from the square root of twice the permittivity times the potential divided by q times the donor concentration: twice 1.04 x 10^-12 times 0.80 = 1.664 x 10^-12, divided by 3.2 x 10^-3 gives 5.2 x 10^-10, whose square root is 2.28 x 10^-5 cm, that is 0.228 micrometre. The field profile is a triangle whose area is the potential, so the peak is twice the potential divided by the width, 1.6/2.28 x 10^-5 = 7.0 x 10^4 V/cm, which is about four times below the avalanche field. The answer 3.5 x 10^4 V/cm drops the factor of two and treats the triangular profile as if it were rectangular.A silicon diode with an ideality factor of 1 carries 0.5 mA at a forward voltage of 0.62 V at 300 K, where the thermal voltage is 25.9 mV. What forward voltage does it need in order to carry 50 mA?
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Answer: D — 0.739 V
Well above the knee the current is proportional to the exponential of V divided by the thermal voltage, so a factor of ten in current costs the natural logarithm of ten times the thermal voltage, 2.303 times 25.9 mV = 59.6 mV. Going from 0.5 mA to 50 mA is two decades, so the voltage rises by 119.2 mV and lands at 0.62 + 0.119 = 0.739 V. Answering 0.680 V counts only one decade, which is the slip of reading the hundredfold ratio as a tenfold one; answering 0.858 V counts four decades. Notice how little the forward voltage moves for a hundredfold current change, which is exactly why a diode makes a poor current limiter and an excellent voltage reference.A voltage reference diode is wanted whose breakdown voltage drifts as little as possible with temperature. Which breakdown voltage should be specified, and why?
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Answer: B — About 6 V, where the negative tunnelling coefficient and the positive avalanche coefficient cancel
The two breakdown mechanisms drift in opposite directions. Tunnelling needs heavy doping on both sides and a depletion region only nanometres wide, and a hotter lattice narrows the band gap and eases tunnelling, giving a negative temperature coefficient below about 5 V. Avalanche needs a wide depletion region, and a hotter lattice scatters carriers more before they can ionise, giving a positive coefficient above about 7 V. Between roughly 5 and 7 V both act together and the two coefficients cancel, which is why precision references are specified at 5.6 to 6.2 V. Choosing 3 V or 12 V picks a region where one mechanism runs unopposed and the drift is at its worst, and the coefficient certainly does depend on the breakdown voltage, which is the whole reason the range exists.A metal-oxide-semiconductor capacitor on a p-type substrate has an oxide capacitance of 345 nF/cm^2, and at the onset of strong inversion its depletion region stops growing at a width of 90 nm. Taking the permittivity of silicon as 1.04 x 10^-12 F/cm, what capacitance per unit area is measured deep in inversion at 1 MHz?
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Answer: C — 86.6 nF/cm^2
The frozen depletion layer contributes a capacitance equal to the permittivity divided by its width, 1.04 x 10^-12 divided by 9 x 10^-6 cm = 115.6 nF/cm^2, and the gate sees that in series with the oxide because the two charge sheets are at different depths. The series value is 345 times 115.6 divided by their sum 460.6, which is 86.6 nF/cm^2, about 25 per cent of the oxide value. Answering 345 nF/cm^2 is the low-frequency result: there the inversion electrons can be generated and removed fast enough to follow the gate and act as the second plate, but in a capacitor with no source or drain to supply them they cannot do so at a megahertz. The 460.6 answer simply adds the two capacitances, which is the rule for elements in parallel and not in series.A bipolar transistor is biased at a collector current of 2 mA with a common-emitter current gain of 150 and an Early voltage of 80 V. Taking the thermal voltage as 25.9 mV, what are its intrinsic voltage gain and its small-signal input resistance looking into the base?
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Answer: A — A gain of 3089 and an input resistance of 1.94 kilo-ohm
Build the two small-signal parameters first. The transconductance is the collector current divided by the thermal voltage, 2 x 10^-3 over 0.0259 = 77.2 mA/V, and the output resistance is the Early voltage divided by the collector current, 80 over 2 x 10^-3 = 40 kilo-ohm. Their product, the intrinsic gain, is 0.0772 times 40000 = 3089, which is also the Early voltage divided by the thermal voltage and is therefore independent of the bias current. The input resistance is the current gain divided by the transconductance, 150/0.0772 = 1.94 kilo-ohm. The value 291 kilo-ohm is the current gain divided by the wrong quantity, namely multiplied by the output resistance instead, and it is far too high for a base node, which is always a low-impedance point compared with a collector.Constant-field scaling divides every length and every voltage by a factor S and multiplies the doping by S, which keeps the internal field and the power density unchanged. In practice the supply and threshold voltages stopped shrinking while the lengths went on shrinking. What then happened to the power density?
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Answer: C — It rose in proportion to S
Work the algebra with the voltage held fixed. Current goes as the aspect ratio times the oxide capacitance per unit area times the square of the voltage, which with fixed voltage scales as S, so power per device scales as S as well. Device area still divides by S squared, so the power per unit area rises as S cubed divided by... more simply, power per device rises as S while area falls as S squared, and the ratio rises as S cubed only if both are counted per device; per unit area of chip the standard result is that power density rises as S rather than staying flat. That is the wall the industry hit: clock frequencies stalled near a few gigahertz because the heat could not be removed, and the response was to stop scaling frequency and start scaling the number of cores. The flat power density in the table holds only while the voltage rows scale with everything else.A photodetector must respond to light at a wavelength of 1.55 micrometre. Using the relation that the cutoff wavelength in micrometres equals 1.24 divided by the band gap in electronvolts, what is the largest band gap a suitable material may have?
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Answer: D — 0.80 eV
A photon can only be absorbed across the gap if its energy is at least the gap, so the longest wavelength a material responds to is the cutoff wavelength, and a material works at 1.55 micrometre only if its cutoff is at least that. Setting 1.24 divided by the gap equal to 1.55 gives a gap of 0.80 eV, and anything larger has its cutoff at a shorter wavelength and is blind here. The value 1.12 eV is the silicon gap, whose cutoff is 1.24/1.12 = 1.107 micrometre, so silicon is exactly the material that cannot see this wavelength — which is why long-haul fibre receivers are built from germanium or indium gallium arsenide instead. Reading the wavelength itself as an energy gives 1.55 eV and confuses the two sides of the relation.A silicon solar cell under steady illumination obeys I = I_L - I_S(exp(V/V_T) - 1), where I_L is the photocurrent. The illumination is then doubled with the temperature held constant, and the thermal voltage is 25.9 mV. Which of the following statements are correct?
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Answer: A — The short-circuit current doubles, because it is simply the photocurrent; B — The open-circuit voltage rises by about 18 mV
Setting the terminal voltage to zero leaves I equal to the photocurrent, so the short-circuit current is directly proportional to illumination and doubles. Setting the current to zero gives the open-circuit voltage as the thermal voltage times the natural logarithm of the photocurrent over the saturation current plus one, so doubling the photocurrent adds only the thermal voltage times the logarithm of two, 0.0259 times 0.693 = 18 mV. Expecting the voltage to double is the tempting symmetry and misses that current is linear in light while voltage is logarithmic in it, which is precisely what makes optical concentration worth doing. The reverse saturation current is a dark parameter set by doping, lifetime and temperature, and illumination does not enter it at all.