Analog Circuits: Diode Circuits, BJT and MOSFET Amplifiers, and Op-amp Circuits

The previous chapter established that β may be anything from 60 to 300 for a part sold as β = 100, and that it drifts with temperature on top of that. So the entire content of biasing is this: design a DC network whose collector current does not care. The voltage-divider (self-bias) circuit is the standard answer, and the mechanism is negative feedback through an emitter resistor. Take V_CC = 12 V, R_1 = 47 kΩ and R_2 = 10 kΩ forming the base divider, R_C = 2.2 kΩ, R_E = 1 kΩ, and V_BE = 0.7 V. Thevenise the divider: V_TH = 12 × 10/57 = 2.105 V and R_TH = 47 ∥ 10 = 8.246 kΩ. The base loop gives I_B = (V_TH − V_BE)/(R_TH + (1 + β)R_E), and at β = 100 that is 1.405/(8246 + 101 000) = 12.86 µA, so I_C = 1.286 mA and I_E = 1.299 mA. Then V_E = 1.299 V, V_C = 12 − 1.286 × 2.2 = 9.170 V, and V_CE = 7.87 V — comfortably in the active region with room to swing both ways, which is the other half of what biasing is for.

MOSFET biasing has the same shape and one important simplification: the gate draws no current, so the divider is unloaded and V_G = V_DD R_2/(R_1 + R_2) exactly, with the resistors free to be megohms. A source resistor then plays the emitter resistor's role, stabilising against the spread in V_T and in µ_nC_ox(W/L) by the same feedback argument. On an integrated circuit neither scheme is used — resistors are expensive and inaccurate in silicon — so devices are biased by current mirrors copying a single reference, which is the subject of a later section. AC coupling is the other half of the DC-versus-AC separation. A coupling capacitor in series with the input and the output passes the signal and blocks DC, so the bias point of the amplifier is unaffected by whatever DC level the source or load happens to sit at, and cascaded stages can each be biased independently. A bypass capacitor across R_E does the reverse: it leaves R_E in place for DC, where the stabilisation is wanted, and shorts it at signal frequencies, where — as the next section computes — it would otherwise cost almost all of the gain. Both are idealised as short circuits in the mid-band analysis, and both come back as low-frequency poles when the band edge is examined.

The small-signal circuit is a different circuit from the bias circuit, and drawing it correctly is most of the work. Three rules make it: every DC supply becomes an AC ground, every coupling and bypass capacitor becomes a short, and the transistor becomes its hybrid-π model — a controlled source g_m v_π with r_π from base to emitter and r_o from collector to emitter. The parameters come from the bias point, which is why the DC analysis had to come first. At I_C = 1.286 mA from the previous section, g_m = I_C/V_T = 1.286 × 10⁻³/0.0259 = 49.7 mA/V and r_π = β/g_m = 100/0.0497 = 2.01 kΩ. Now compute the common-emitter voltage gain with the emitter resistor bypassed, so the emitter is at AC ground: A_v = −g_m R_C = −0.0497 × 2200 = −109. Input resistance is R_TH ∥ r_π = 8.246 ∥ 2.013 = 1.62 kΩ — note how much lower that is than the R_TH you might expect, because r_π dominates. Output resistance is R_C ∥ r_o ≈ R_C when r_o is large.

The MOSFET version runs identically with g_m = √(2 µ_nC_ox(W/L) I_D) in place of I_C/V_T. Take a common-source stage at I_D = 0.5 mA with µ_nC_ox(W/L) = 2 mA/V² and V_T = 0.5 V. Then V_ov = √(2I_D/k) = √(2 × 0.5/2) = 0.707 V, so V_GS = 1.207 V, and g_m = k V_ov = 1.414 mA/V. With λ = 0.02 V⁻¹, r_o = 1/λI_D = 100 kΩ, and with a drain resistor R_D = 10 kΩ the gain is A_v = −g_m(R_D ∥ r_o) = −1.414 × 10⁻³ × 9.091 × 10³ = −12.9. Compare that with a BJT at the same 0.5 mA, where g_m = 0.5 × 10⁻³/0.0259 = 19.3 mA/V, 13.7 times larger. That ratio is the single most important structural difference between the two devices in an amplifier, and it comes from the different laws: g_m ∝ I_C for the exponential BJT and g_m ∝ √I_D for the square-law MOSFET. So quadrupling a MOSFET's transconductance costs sixteen times the bias current, while quadrupling a BJT's costs four times. The MOSFET pays that back with an infinite gate resistance, a threshold that can be engineered, and a device that is a switch as well as an amplifier — which is why MOS won digital outright while bipolar survives wherever g_m per microamp is what matters.

An AC-coupled amplifier has a mid-band where the gain is flat, and two edges. At the low edge the coupling and bypass capacitors are no longer shorts, and each contributes a pole at f = 1/2πRC where R is the resistance that capacitor actually sees with all other capacitors shorted. The overall low cutoff is dominated by the highest of those poles, and this is where intuition misleads: it is not set by the smallest capacitor. Return to the biased amplifier. The input coupling capacitor C_C = 10 µF sees the source resistance 600 Ω in series with R_in = 1.62 kΩ, that is 2.22 kΩ, giving a pole at 1/(2π × 2218 × 10 × 10⁻⁶) = 7.18 Hz. The emitter bypass capacitor C_E = 100 µF is ten times larger, so it ought to matter less — but the resistance it sees is R_E ∥ (r_π + R_TH)/(1 + β) = 1000 ∥ (10 259/101) = 1000 ∥ 101.6 = 92.2 Ω, twenty-four times smaller, because looking into the emitter divides the base-circuit resistance by (1 + β). Its pole is therefore 1/(2π × 92.2 × 100 × 10⁻⁶) = 17.3 Hz — higher than the coupling capacitor's, and so it is the bypass capacitor that sets the low cutoff. Compute the resistance each capacitor sees before deciding which one dominates; the capacitance alone tells you nothing.

On an integrated circuit, resistors are inaccurate and area-hungry but matched transistors are nearly free, so bias currents are distributed by copying rather than by dividing voltages. A current mirror is two transistors sharing a gate-source (or base-emitter) voltage: force a reference current through the first, which is diode-connected so that it develops whatever V_GS that current requires, and the second — seeing the identical V_GS — carries the same current scaled by the ratio of the device sizes. With I_ref = 100 µA and (W/L)_2/(W/L)_1 = 4, I_out = 400 µA. Two non-idealities are examinable. First, the output is not a perfect current source: its output resistance is r_o2 = 1/λI_out = 1/(0.02 × 400 × 10⁻⁶) = 125 kΩ, and because of channel-length modulation the copy is only exact when both devices have the same V_DS. With V_DS1 = 1.2 V and V_DS2 = 3 V at λ = 0.02 V⁻¹, the ratio is (1 + 0.06)/(1 + 0.024) = 1.035, a 3.5 per cent error from nothing but drain-voltage mismatch. The cure is the cascode mirror, which stacks a second device to hold V_DS steady and multiplies the output resistance by roughly g_m r_o ≈ 141, giving about 17.7 MΩ. Second, in a BJT mirror the base currents come out of the reference: I_out/I_ref = 1/(1 + 2/β), which at β = 100 is 0.980 — a 2 per cent systematic error that the emitter-follower (beta-helper) mirror removes by supplying the base current from a third transistor.

A differential amplifier is two matched devices sharing a tail current source, and it is the input stage of essentially every op-amp because it responds to the difference of its two inputs and rejects what they have in common. Take a MOS pair with a tail current I_SS = 200 µA, so 100 µA in each device, with µ_nC_ox(W/L) = 2 mA/V². Then g_m = √(2 × 2 × 10⁻³ × 100 × 10⁻⁶) = 0.632 mA/V, and with drain resistors R_D = 20 kΩ the differential gain from v_id to the differential output is A_d = −g_m R_D = −12.65. Now the common-mode behaviour, which is what the topology is for. Raise both inputs together and both devices try to conduct more, but the tail source resists, so the common-mode gain is suppressed by the tail's output resistance: A_cm ≈ −R_D/2R_SS for a single-ended output. The common-mode rejection ratio works out beautifully simply as CMRR = g_m R_SS. With a resistive tail of R_SS = 500 kΩ, CMRR = 0.632 × 10⁻³ × 5 × 10⁵ = 316, or 50.0 dB. Replace that resistor with a current mirror of output resistance 5 MΩ and CMRR = 3162, or 70.0 dB — a factor of ten in tail resistance is exactly 20 dB of rejection, and that is the whole reason the tail is a current source rather than a resistor.

An ideal op-amp has infinite gain, infinite input resistance and zero output resistance, and every linear op-amp circuit follows from two consequences of that. Because the gain is infinite and the output is finite, the differential input voltage must be zero — the inputs are at the same potential, a virtual short — and because the input resistance is infinite, no current flows into either terminal. Apply both to the inverting amplifier, with R_1 from the source to the inverting input and R_2 from there to the output, the non-inverting input grounded. The inverting node is therefore at 0 V, a virtual ground, so the current through R_1 is v_i/R_1; none of it enters the op-amp, so all of it flows on through R_2; hence v_o = −(R_2/R_1)v_i. With R_1 = 1 kΩ and R_2 = 47 kΩ the gain is −47, and the input resistance seen by the source is exactly R_1 = 1 kΩ — a real limitation, and the reason the non-inverting configuration, gain 1 + R_2/R_1, is preferred when the source cannot be loaded. It is worth checking what finite gain costs: at open-loop A = 10⁵, the closed-loop gain is −47/(1 + 48/10⁵) = −46.977, an error of 0.048 per cent. That is why the ideal analysis is not an approximation to apologise for.

The virtual ground has one more property that makes the summing amplifier almost trivial: because the inverting node is held at 0 V no matter what, each input resistor delivers a current that depends only on its own source, so the inputs cannot interact. Connect V_1 through R_1 and V_2 through R_2 to the same virtual ground with feedback R_f, and v_o = −(R_f/R_1)V_1 − (R_f/R_2)V_2. With R_f = 10 kΩ, R_1 = 10 kΩ, R_2 = 2 kΩ, V_1 = 1 V and V_2 = 0.5 V, v_o = −(1 × 1 + 5 × 0.5) = −3.5 V. Independent weights on independent inputs, with no cross-talk — which is why this circuit is an audio mixer, a digital-to-analogue converter's binary-weighted network, and the summing junction of every analogue controller. The corresponding non-inverting summer does not have this property: its inputs sit on a resistive network with no node held at a fixed potential, so the weights depend on all the resistors at once and changing one changes them all. That asymmetry is a favourite examination point, and the reason the inverting form is the one used in practice.

Replace the feedback resistor of an inverting amplifier with a capacitor and the same virtual-ground argument gives an integrator. The input current v_i/R has nowhere to go but into C, so v_o = −(1/RC)∫v_i dt, and in the frequency domain the gain is −1/jωRC, falling at 20 dB per decade with the unity-gain frequency at 1/2πRC. With R = 10 kΩ and C = 10 nF, RC = 100 µs and that frequency is 1592 Hz. Feed in a 1 V step and the output ramps at −V_i/RC = −10 V per millisecond, reaching −10 V after 1 ms — which is how a ramp generator and the integrating half of a dual-slope ADC are built. Swap the two components — capacitor at the input, resistor in feedback — and you have a differentiator, v_o = −RC (dv_i/dt), whose gain rises at 20 dB per decade. With the same R and C, a 1 V peak-to-peak triangular wave at 1 kHz has a slope of 2 V per half period = 4000 V/s, so the output is a square wave of −10⁻⁴ × 4000 = ∓0.4 V. Both circuits are exact within the ideal-op-amp assumption, and both are unusable as written.

Active filters put those same RC networks around an op-amp to get responses a passive network cannot: gain, a low output impedance, no inductors, and stages that do not load one another. A first-order active low-pass is simply an inverting amplifier with a capacitor across the feedback resistor — mid-band gain −R_2/R_1, pole at 1/2πR_2C_2. Second-order responses need two energy-storage elements and some positive feedback, and the standard form is the Sallen–Key low-pass: two series Rs, a capacitor from the mid-node to ground, a capacitor from the mid-node to the output, and a non-inverting amplifier of gain K closing the loop. With equal components, f_0 = 1/2πRC — with R = 10 kΩ and C = 10 nF that is again 1592 Hz — and the quality factor is Q = 1/(3 − K). This is the design equation worth internalising because it says something structural. A maximally flat Butterworth response needs Q = 1/√2 = 0.707, so 3 − K = 1.414 and K = 1.586, that is a feedback ratio R_b/R_a = 0.586. Now watch what happens as K rises: at K = 2.5, Q = 2 and the response peaks; at K = 2.9, Q = 10 and it peaks sharply; at K = 3 exactly, Q is infinite and the filter oscillates. The same expression that designs a filter designs an oscillator, and the boundary between the two is a single number in the gain-setting divider. That is not a curiosity to note in passing — it is the reason the next section exists, and it is why a high-Q active filter must be built with tight resistor tolerances: a 5 per cent error in K near K = 2.9 moves Q by tens of per cent.

Every circuit so far used negative feedback. A Schmitt trigger uses positive feedback deliberately, and its purpose is to make a comparator decide. A plain comparator has one threshold, so an input creeping slowly through it — or an input with any noise on it — produces an output that chatters back and forth across the transition. Feed a fraction of the output back to the non-inverting input and the threshold moves away from the input as soon as the output changes, so a single crossing produces a single clean transition. Take an inverting Schmitt trigger with output saturation at ±12 V and a feedback divider of R_1 = 10 kΩ from the non-inverting input to ground and R_2 = 90 kΩ from it to the output. The feedback fraction is β = R_1/(R_1 + R_2) = 0.1, so the non-inverting input sits at 0.1 × (±12) = ±1.2 V. When the output is high the threshold is +1.2 V; the instant the input exceeds it the output slams to −12 V and the threshold drops to −1.2 V. The upper and lower trip points are therefore +1.2 V and −1.2 V, and the hysteresis — the gap between them — is 2.4 V. Any noise smaller than 2.4 V peak-to-peak now cannot cause a false transition, which is the whole point. Note what hysteresis costs: the transition no longer happens at a single input level, so a Schmitt trigger adds a deliberate, known input-dependent delay. It is a squarer and a noise gate, not a precision comparator.

Close a loop from that Schmitt trigger's output back to its inverting input through an RC and the circuit oscillates with no input at all — a relaxation (astable) oscillator. The capacitor charges toward whichever rail the output is at, reaches the trip point, flips the output, and starts charging the other way, so the period is T = 2RC ln((1 + β)/(1 − β)). With β = 0.1, R = 10 kΩ and C = 10 nF, T = 2 × 10⁻⁴ × ln(1.1/0.9) = 2 × 10⁻⁴ × 0.2007 = 40.1 µs, that is f = 24.9 kHz. Note that the frequency depends only on R, C and the divider ratio — the supply voltage cancels out, because both the rail the capacitor charges toward and the threshold it must reach scale with it. Sinusoidal oscillators work on a different principle, the Barkhausen criterion: a loop whose gain has magnitude exactly 1 and total phase shift exactly 0° (or 360°) will sustain a sinusoid at that one frequency. The two examples in the syllabus are worth having as numbers. The Wien bridge uses a series RC and a parallel RC in the feedback path, whose attenuation is exactly 1/3 with zero phase shift at f_0 = 1/2πRC — 1592 Hz for R = 10 kΩ, C = 10 nF — so the amplifier's non-inverting gain must be exactly 3, that is R_f/R_i = 2. The RC phase-shift oscillator uses three identical RC sections to accumulate 180° of phase, which happens at f_0 = 1/(2πRC√6) = 650 Hz for the same components, where the three sections attenuate by 1/29, so the inverting amplifier needs a gain of −29.

Negative feedback is only negative while the loop's phase shift is small. Every pole in the loop contributes up to 90° of lag, so a multi-stage amplifier with two or more poles inside the loop will, at some frequency, have shifted the phase by 180° — at which point the feedback is positive, and if the loop gain is still above unity there, the amplifier oscillates. Phase margin measures the distance from that fate: it is 180° − |∠A(f)β| evaluated at the frequency where the loop gain magnitude passes through unity. Take an uncompensated amplifier with DC gain A_0 = 10⁵, a first pole at 1 MHz and a second at 10 MHz, used as a unity-gain follower so that β = 1. The gain crosses unity at A_0 × p_1 = 10¹¹ Hz — a hundred gigahertz, four decades above the second pole, where both poles have contributed their full 90° and the phase shift is 180°. Phase margin zero: the circuit will oscillate, and no choice of external components will stop it. The problem is not that the amplifier is too slow but that it has too much gain left at too high a frequency, and the cure is to throw gain away on purpose.

Dominant-pole compensation deliberately moves the first pole down until the loop gain has fallen to unity before the second pole can contribute much phase. Choose the new first pole so that unity gain occurs exactly at the second pole: A_0 p_1' = 10 MHz, so p_1' = 10 × 10⁶/10⁵ = 100 Hz. At that crossover frequency the dominant pole has contributed its full 90° and the second pole, being exactly at the crossover, contributes 45°, for a total of 135°. Phase margin = 180° − 135° = 45° — stable, but with about 2 dB of closed-loop peaking and a step response that overshoots by roughly 20 per cent. For the usual design target of 60° of phase margin the second pole may contribute only 30°, and since a pole contributes arctan(f/p), that requires f_u = p_2 tan 30° = 10 MHz × 0.5774 = 5.77 MHz, hence p_1' = 5.77 × 10⁶/10⁵ = 57.7 Hz. Two things to read off. First, the compensated amplifier's gain-bandwidth product is that unity-gain frequency, so a 5.77 MHz f_u means a closed-loop gain of 10 has a bandwidth of 577 kHz — the stability was bought with bandwidth, one for one. Second, phase margin depends on the feedback factor: at β = 1 the loop gain is largest and the margin smallest, so an op-amp that is stable at a closed-loop gain of 10 may oscillate as a unity-gain follower. That is exactly why datasheets say 'unity-gain stable' as a distinct specification, and why decompensated op-amps exist which trade unity-gain stability for more bandwidth at higher closed-loop gains.