Analog and Digital Electronics: Diodes, Transistors, Op-Amp Circuits, Logic, Data Converters and the Microprocessor
2. Operational-amplifier circuits
With negative feedback an ideal op-amp obeys two rules: no current enters either input, and the two inputs sit at the same voltage (the virtual short). Every standard circuit follows from them.
| Circuit | Output | Note |
|---|---|---|
| Inverting amplifier | v_o = −(R_f/R_i)v_i | input resistance R_i |
| Non-inverting amplifier | v_o = (1 + R_f/R_i)v_i | very high input resistance |
| Buffer (voltage follower) | v_o = v_i | isolates a high-impedance source from its load |
| Adder (inverting summer) | v_o = −R_f(v₁/R₁ + v₂/R₂ + …) | equal resistors give −(v₁ + v₂ + …) |
| Difference amplifier (subtractor) | v_o = (R₂/R₁)(v₂ − v₁) | needs matched resistor ratios; resistor mismatch sets its CMRR |
| Integrator | v_o = −(1/RC)∫v_i dt | a constant input gives a ramp; a resistor across C limits dc gain |
| Differentiator | v_o = −RC dv_i/dt | gain rises with frequency, so it amplifies noise |
| Three-op-amp instrumentation amplifier | v_o = (1 + 2R/R_G)(R₄/R₃)(v₂ − v₁) | gain set by one resistor R_G; very high input impedance and CMRR |
The common-mode rejection ratio CMRR = A_d/A_cm, usually quoted as 20 log₁₀(A_d/A_cm) dB. It matters more in biomedical work than anywhere else: the body picks up mains voltage of the order of volts common to every electrode, while the ECG between two electrodes is about 1 mV. The output interference is A_cm × v_cm = (A_d/CMRR) × v_cm, so a 100 dB CMRR with A_d = 1000 turns 1 V of common-mode pickup into 10 mV at the output, beside a 1 V ECG.
Filters and generators. A first-order active low-pass (R_f ∥ C_f in the feedback of an inverting stage) has corner 1/(2πR_fC_f); a Sallen–Key stage gives a second-order response with one op-amp. A Schmitt trigger — a comparator with positive feedback fraction β = R₂/(R₁ + R₂) — switches at ±βV_sat, and that hysteresis of 2βV_sat keeps a noisy input from chattering. Closing an RC network around it gives an astable multivibrator of period 2RC ln[(1 + β)/(1 − β)]. A Wien-bridge oscillator runs at f = 1/(2πRC) with a non-inverting gain of exactly 3. The 555 timer as an astable has t_high = 0.693(R_A + R_B)C, t_low = 0.693R_BC and duty cycle (R_A + R_B)/(R_A + 2R_B).
3. Number systems, Boolean algebra and combinational logic
Binary, octal (groups of three bits) and hexadecimal (groups of four) are positional; BCD codes each decimal digit in four bits. In 2’s complement an n-bit word spans −2n−1 to 2n−1 − 1, the most significant bit carries weight −2n−1, and a number is negated by inverting every bit and adding 1: 11110110 is −128 + 118 = −10. Boolean algebra adds De Morgan’s laws (A + B)′ = A′B′ and (AB)′ = A′ + B′ to the ordinary identities, and a Karnaugh map groups adjacent 1s in powers of two to minimise a sum of products.
| Block | What it does | Size rule |
|---|---|---|
| Half adder / full adder | S = A ⊕ B, C = AB; full adder S = A ⊕ B ⊕ C_in, C_out = AB + C_in(A ⊕ B) | n full adders ripple for n bits |
| Magnitude comparator | outputs A > B, A = B, A < B | equality bit i: (A_i ⊕ B_i)′ |
| Decoder | activates one of 2^n outputs for an n-bit input | n-to-2^n; used for memory chip select |
| Encoder / priority encoder | 2^n inputs to an n-bit code; priority version resolves several active inputs | 2^n-to-n |
| MUX / DEMUX | selects one of 2^n inputs onto one line / routes one line to one of 2^n outputs | n select lines; a 2^n:1 MUX realises any function of n + 1 variables |
Multivibrators are the regenerative circuits: the bistable has two stable states and is the flip-flop (SR, D, JK, T); the monostable has one stable state and returns to it after a fixed pulse width, which makes it a timer; the astable has none and oscillates. The Schmitt trigger belongs here too, as a bistable whose state is set by the input level with two different thresholds.
4. Principles of ADC and DAC
An n-bit converter over a full-scale range V_FS resolves 1 LSB = V_FS/2^n. A DAC produces V_o = V_ref × D/2^n for an input code D (some texts use 2^n − 1 in the denominator when the maximum code must equal V_ref exactly; read the question’s definition). The binary-weighted resistor DAC needs resistors spanning a 2n−1 ratio, hard to make accurately; the R-2R ladder uses only two values and is the practical choice.
| Type | Principle | Conversion time | Where used |
|---|---|---|---|
| Flash | 2^n − 1 comparators against a resistor ladder, all at once | one step — fastest | very high speed, low resolution |
| Successive approximation (SAR) | binary search, one bit per clock using a DAC and one comparator | n clock cycles | general-purpose data acquisition |
| Counter (ramp) | counts up until the DAC output passes the input | up to 2^n cycles | simple, slow |
| Dual-slope integrating | integrates the input for a fixed time, then de-integrates a reference | slow | digital meters; rejects mains if the window is a multiple of 20 ms |
| Sigma-delta | 1-bit modulator at high oversampling plus digital filter | moderate | high-resolution biopotential and audio |
Quantisation error is at most ±½ LSB, and for a full-scale sine the ideal signal-to-quantisation-noise ratio is 6.02n + 1.76 dB — each extra bit buys about 6 dB. A sample-and-hold ahead of the ADC freezes the input during conversion, since a SAR converter needs the input steady for all n steps.
5. The microprocessor: architecture and interfacing
The 8085 is an 8-bit microprocessor: an 8-bit data bus and ALU, a 16-bit address bus addressing 2^16 = 64 KB, general-purpose registers B, C, D, E, H, L (usable as pairs BC, DE, HL), the accumulator A, a flag register (sign, zero, auxiliary carry, parity, carry), and 16-bit stack pointer and program counter. The low address byte shares pins AD0–AD7 with the data bus; the ALE signal marks the address phase so an external latch can hold A0–A7 while the same pins carry data. A timing-and-control unit issues RD, WR and IO/M.
- Memory interfacing. A chip of 2^k locations uses k address lines directly; the remaining high-order lines go to a decoder that generates its chip select. An 8 KB chip needs 13 lines, and placed at 4000H it occupies 4000H–5FFFH.
- I/O-mapped I/O uses IN and OUT instructions with an 8-bit port address, so up to 256 input and 256 output ports, selected with IO/M high. Memory-mapped I/O treats a port as a memory location, so every memory instruction can reach it, at the cost of address space.
- Interrupts: TRAP is non-maskable and highest priority, then RST 7.5, 6.5 and 5.5 (maskable, vectored) and INTR (maskable, the device supplies the vector). A programmable peripheral interface such as the 8255 adds three 8-bit parallel ports; DMA lets a controller move blocks of data while the processor releases the buses.
Key takeaways
- BJT amplifies with B-E forward and B-C reverse biased, g_m = I_C/V_T; MOSFET saturation I_D = ½k′(W/L)(V_GS − V_t)².
- Virtual short plus no input current gives every op-amp circuit; the instrumentation amplifier gain is (1 + 2R/R_G) × the difference-stage gain.
- Output interference = (A_d/CMRR) × v_cm; CMRR in dB is 20 log(A_d/A_cm).
- 2^n:1 MUX needs n select lines; flash ADC needs 2^n − 1 comparators; SAR takes n clocks; LSB = V_FS/2^n.
- 8085: 16 address lines (64 KB), AD0–AD7 multiplexed via ALE, TRAP non-maskable, 256 I/O-mapped ports.
Practice questions (15)
Attempt each one before opening the answer. Every explanation names the tempting wrong option as well as the right one, because that is where marks are lost.
For an npn BJT to operate as a linear amplifier, its junctions must be biased as
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Answer: A — base-emitter forward, base-collector reverse
The active region needs the emitter junction forward biased to inject carriers and the collector junction reverse biased to collect them, giving I_C = βI_B. Both forward is saturation (a closed switch), both reverse is cut-off, and the last combination is the inefficient inverse-active mode.An inverting amplifier has R_f = 100 kΩ and R_i = 10 kΩ. For an input of +0.2 V dc, the output (in V) is ____.
Numerical answer — type the value.
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Answer: -2
v_o = −(R_f/R_i)v_i = −10 × 0.2 = −2 V. Dropping the sign gives +2 V; the non-inverting formula (1 + R_f/R_i) would give +2.2 V. Type the answer as -2.An ECG amplifier has differential gain 1000 and common-mode gain 0.01. Its CMRR (in dB) is ____.
Numerical answer — type the value.
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Answer: 100
CMRR = A_d/A_cm = 1000/0.01 = 10⁵, and 20 log₁₀ 10⁵ = 100 dB. Using 10 log gives 50 dB, which treats a voltage ratio as a power ratio.A biopotential amplifier has differential gain 1000 and a CMRR of 100 dB. The patient carries 1 V (rms) of 50 Hz common-mode interference while the ECG between the electrodes is 1 mV. The interference at the output (in mV rms) is ____.
Numerical answer — type the value.
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Answer: 10
CMRR = 10⁵, so A_cm = A_d/CMRR = 1000/10⁵ = 0.01 and the output interference is 0.01 × 1 V = 10 mV, against a 1 V amplified ECG. Taking A_cm = 1/CMRR (forgetting A_d) gives 0.01 mV; multiplying by A_d as if the interference were differential gives 1000 V.A constant positive dc voltage is applied to an ideal op-amp integrator (inverting type). Its output is
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Answer: A — a ramp falling linearly with time until the op-amp saturates
v_o = −(1/RC)∫V dt = −Vt/RC, a straight line of slope −V/RC, which continues until the output hits the negative supply rail. A constant output would be an inverting amplifier; an exponential appears only if a resistor is placed across the capacitor.The 8-bit 2’s-complement word 11110110 represents the decimal number ____.
Numerical answer — type the value.
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Answer: -10
The MSB has weight −128 and the rest is 64 + 32 + 16 + 4 + 2 = 118, so the value is −128 + 118 = −10; equivalently invert (00001001) and add 1 to get 00001010 = 10. Reading it as unsigned gives 246, and as sign-magnitude gives −118. Type the answer as -10.The number of select lines needed by a 16-to-1 multiplexer is
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Answer: A — 4
2^n inputs need n select lines, and 16 = 2^4. Sixteen is the number of data inputs, and 8 would be half of them.An 8-bit DAC has V_ref = 5.12 V and output V_ref × D/256. Its resolution (in mV) is ____.
Numerical answer — type the value.
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Answer: 20
1 LSB = 5.12 V/2⁸ = 5.12/256 = 0.02 V = 20 mV. Dividing by 8 (the bit count) gives 640 mV, and dividing by 255 gives 20.08 mV, which is not the definition stated.An ECG front end has gain 1000 followed by a 12-bit ADC spanning −5 V to +5 V. The smallest change in the electrode voltage that the system resolves (one LSB referred to the input, in µV), to two decimal places, is ____.
Numerical answer — type the value.
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Answer: 2.44
The ADC LSB is 10 V/4096 = 2.441 mV at the ADC input; dividing by the gain of 1000 refers it to the electrodes as 2.44 µV. Using 5 V instead of the 10 V span gives 1.22 µV, and forgetting the gain gives 2441 µV.The number of comparators in an 8-bit flash ADC is
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Answer: A — 255
A flash converter compares the input against every one of the 2^n − 1 = 255 thresholds between its 256 output codes. 256 counts codes rather than thresholds, and 8 is what a SAR converter needs in clock cycles, not comparators.Which statements about the 8085 microprocessor are correct?
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Answer: A — its 16-bit address bus addresses 64 KB of memory; B — AD0–AD7 carry both the low address byte and data, separated using ALE; D — with I/O-mapped I/O, an 8-bit port address allows up to 256 input ports
2^16 = 65 536 bytes; the lower address byte is time-multiplexed on AD0–AD7 and latched when ALE is high; IN and OUT carry an 8-bit port address, so 256 ports each way. TRAP is the one interrupt that cannot be masked, which is why it is reserved for events such as power failure.An 8 KB EPROM is interfaced to the 8085 starting at address 4000H. The number of address lines connected directly to the chip is ____.
Numerical answer — type the value.
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Answer: 13
8 KB = 8192 = 2^13 locations, so A0–A12 go to the chip and A13–A15 feed the chip-select decoder; the chip spans 4000H–5FFFH. Sixteen counts every processor line, and 8 confuses the data width with the address width.An op-amp Schmitt trigger uses positive feedback with fraction β = R₂/(R₁ + R₂). Which statements are correct?
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Answer: A — its transfer characteristic shows hysteresis; B — it relies on positive feedback; C — increasing β widens the hysteresis band
Positive feedback makes the output snap between ±V_sat, and the thresholds ±βV_sat differ for rising and falling inputs, giving a hysteresis width of 2βV_sat that grows with β. It is a regenerative switching circuit, not a linear amplifier; 1/β is the gain of a non-inverting amplifier with negative feedback.A 555 timer in astable mode has R_A = 1 kΩ, R_B = 10 kΩ and C = 0.1 µF. Its duty cycle (in %), to one decimal place, is ____.
Numerical answer — type the value.
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Answer: 52.4
t_high = 0.693(R_A + R_B)C and t_low = 0.693R_BC, so the duty cycle is (R_A + R_B)/(R_A + 2R_B) = 11/21 = 52.4%; the period 0.693 × 21 kΩ × 0.1 µF = 1.455 ms gives about 687 Hz. R_B/(R_A + 2R_B) = 47.6% is the low-time fraction, not the duty cycle.An n-channel enhancement MOSFET in saturation has k′(W/L) = 2 mA/V², V_t = 1 V and V_GS = 3 V. Its drain current (in mA) is ____.
Numerical answer — type the value.
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Answer: 4
I_D = ½k′(W/L)(V_GS − V_t)² = ½ × 2 × (2)² = 4 mA, and g_m = 2I_D/(V_GS − V_t) = 4 mA/V. Forgetting the ½ gives 8 mA; squaring V_GS instead of the overdrive gives 9 mA.